Texas Instruments TPS6381 EVM Series, Руководство пользователя

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17 SLVUBK9A – July 2019 – Revised October 2019
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TPS6381xEVM
6.5 VOUT2 Register (Address = 5h) [reset = 42h]
Table 9 shows the VOUT2 register.
Return to Summary Table .
This register sets the device output voltage when the VSEL pin is high. This register is volatile, so it loses
its contents if the voltage on the VIN pin becomes less than the UVLO threshold or a low logic level is
applied to the EN pin.
Table 9. VOUT2 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0b Reserved
6-0 VOUT2 R/W 1000010b These bits set the output voltage of the converter when the VSEL pin
is low.
When the RANGE bit = 0, the output voltage in volts is
1.8 + (VOUT2 × 0.025).
When the RANGE bit = 1, the output voltage in volts is
2.025 + (VOUT2 × 0.025).