Texas Instruments TPS6381 EVM Series, Руководство пользователя

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Register Map
13 SLVUBK9A – July 2019 – Revised October 2019
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TPS6381xEVM
6.1 CONTROL Register (Address = 1h) [reset = X]
Table 5 shows the CONTROL register.
Return to Summary Table .
This register configures the device. This register is volatile, so it loses its contents if the voltage on the VIN
pin becomes less than the UVLO threshold or a low logic level is applied to the EN pin.
Table 5. CONTROL Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0b This bit is reserved for future use and must be programmed to 0.
6 RANGE R/W 0b This bit selects the output voltage range.
0b = low range (1.8 V to 4.975 V)
1b = high range (2.025 V to 5.2 V)
5 ENABLE R/W X This bit enables and disables the converter.
In the TPS63810 the reset value of this bit is 1.
In the TPS63811 the reset value of this bit is 0.
0b = converter is disabled
1b = converter is enabled
4 RESERVED R/W 0b This bit is reserved for future use and must be programmed to 0.
3 FPWM R/W 0b This bit controls forced-PWM operation.
0b = forced-PWM operation disabled
1b = forced-PWM operation enabled
2 RPWM R/W 0b This bit controls ramp-PWM operation.
0b = ramp-PWM disabled
1b = ramp-PWM enabled
1-0 SLEW R/W 00b These bits control the slew rate of the converter when the output
voltage setting is changed to a new value.
00b = 1 V/ms
01b = 2.5 V/ms
10b = 5 V/ms
11b = 10 V/ms