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Board Layout
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SLUUBZ4 – February 2019
Copyright © 2019, Texas Instruments Incorporated
TPS562231EVM 2-A, Synchronous step-down converter evaluation module
5
Board Layout
This section provides a description of the TPS562231EVM, board layout, and layer illustrations.
5.1
Layout
The board layout for the TPS562231EVM is shown in
and
. The top layer
contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the
pins of the TPS562231 and a large area filled with ground. Most of the signal traces are also located on
the top side. The input decoupling capacitors, C1, C2, and C3 are located as close to the IC as possible.
The input and output connectors, test points, and all of the components are located on the top side. The
bottom layer is a ground plane along with the switching node copper fill, signal ground copper fill and the
feed back trace from the point of regulation to the top of the resistor divider network.
Figure 6. Top Assembly