Board Layout
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5
Board Layout
This section provides a description of the TPS560200EVM-537, board layout, and layer illustrations.
5.1
Layout
The board layout for the TPS560200EVM-537 is shown in
Figure 15
through
Figure 17
. The top layer
contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the
pins of the TPS560200 and a large area filled with ground. All of the signal traces also are located on the
top side. The input decoupling capacitors, C1 and C2, are located as close to the IC as possible. The
input and output connectors, test points, and all of the components are located on the top side. The
bottom layer is a ground plane.
Figure 15. Top Assembly
12
TPS560200EVM-537 0.5-A, Single Channel Regulator Evaluation Module
SLVU954 – September 2013
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