Board Layout
14
SLVUAM8A – December 2015 – Revised March 2019
Copyright © 2015–2019, Texas Instruments Incorporated
TPS54A20EVM-770, 10-A, SWIFT™ regulator evaluation module
3
Board Layout
This section provides a description of the TPS54A20EVM-770 board layout and layer illustrations.
3.1
Layout
The board layout for the TPS54A20EVM-770 is shown in
through
. The top-side layer
of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-
oz. copper.
The top layer contains the main power traces for VIN, V
OUT
, SWA and SWB. Also on the top layer are
connections for the remaining pins of the TPS54A20 and a large area filled with ground. The internal
layer-1 is dedicated ground plane. The internal layer-2 contain an additional large ground copper area as
well as an additional V
OUT
copper fill. The bottom layer is another ground plane with an additional trace for
the output voltage feedback. The top-side ground traces are connected to the bottom and internal ground
planes with multiple vias placed around the board including five vias directly under the TPS54A20 device
to provide a thermal path from the top-side ground plane to the bottom-side ground plane.
The input decoupling capacitors and bootstrap capacitor are all located as close to the IC as possible.
Additionally, the voltage setpoint resistor divider components are kept close to the IC. The voltage divider
network ties to the output voltage at the point of regulation, the copper V
OUT
trace at the TP7 test point. For
the TPS54A20, an additional input bulk capacitor may be required, depending on the EVM connection to
the input supply. Critical analog circuits such as the voltage set point divider, frequency set resistor, and
compensation components are terminated to ground using a wide ground trace separate from the power
ground pour.
Figure 16. TPS54A20EVM-770 Top-Side Assembly
Figure 17. TPS54A20EVM-770 Top-Side Layout