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EVM IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:

This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY
 and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.

Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified  (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive
.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein
.

Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.

Persons handling the product must have electronics training and observe good laboratory practice standards.

No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright 

 2003, Texas Instruments Incorporated

Содержание TPS54380EVM-001

Страница 1: ...June 2003 PMP Systems Power User s Guide SLVU087...

Страница 2: ...itute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual p...

Страница 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...

Страница 4: ...t If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 55 C The EVM is...

Страница 5: ...sults Chapter 3 Board Layout Chapter 4 Schematic and Bill of MAterials Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A c...

Страница 6: ...Information About Cautions and Warnings vi Trademarks SWIFT is a trademark of Texas Instruments PowerPAD is a trademark of Texas Instruments...

Страница 7: ...2 1 2 1 Input Output Connections 2 2 2 2 Efficiency 2 3 2 3 Power Dissipation 2 4 2 4 Output Voltage Regulation 2 5 2 5 Load Transients 2 6 2 6 Loop Characteristics 2 7 2 7 Output Voltage Ripple 2 8...

Страница 8: ...pple TPS54380 2 9 2 11 Power Up With Tracking 2 10 2 12 Powering Down With Tracking 2 11 2 13 Powering Up With Rationmetric Sequencing 2 12 2 14 Powering Down With Ratiometric Sequencing 2 12 2 15 Pow...

Страница 9: ...port documentation for the TPS54380EVM 001 evaluation module HPA001 The TPS54380EVM 001 performance specifications are given with the schematic and bill of material for the TPS54380EVM 001 Topic Page...

Страница 10: ...ackage This eliminates the need for external MOSFETs and their associated drivers The low drain to source on resistance of the MOSFETs gives the TPS54380 high efficiency and helps to keep the junction...

Страница 11: ...erformance Specification Summary Specification Test Conditions Min Typ Max Units Input voltage range 3 0 3 3 or 5 0 5 5 V Output voltage set point 0 9 1 8 3 3 V Output current range VI 3 V to 5 5 V 3...

Страница 12: ...W 0 891 V V O 0 891 V Table 1 3 Output Voltage Programming Output Voltage V R2 Value k 0 9 1000 1 2 28 7 1 5 14 7 1 8 9 76 2 5 5 49 3 3 3 74 The minimum output voltage is limited by the minimum contro...

Страница 13: ...d at C1 1 3 1 Power Sequencing By selecting different R6 R7 resistor divider ratios different power sequencing scenarios can be set The equations 1 3 1 4 and 1 5 below show how to select the different...

Страница 14: ...1 6...

Страница 15: ...S54380EVM 001 and covers efficiency output voltage regulation load transients loop response output ripple input ripple and start up Topic Page 2 1 Input Output Connections 2 2 2 2 Efficiency 2 3 2 3 P...

Страница 16: ...80 is intended to be used as a point of load regulator In typical applications it is usually located close to the input voltage source When using the TPS54380EVM 001 with an external power supply as t...

Страница 17: ...emperature of 25 C The efficiency is lower at higher ambient temperatures due to temperature variation in the drain to source resistance of the MOSFETs The efficiency is slightly lower at 700 kHz than...

Страница 18: ...junction temperature is approximately 60 C while the case temperature is approximately 55 C The total circuit losses at 25 C are shown in Figure 2 3 Power dissipation is shown for input voltages of 3...

Страница 19: ...5 Measurements are given for an ambient temperature of 25 C Figure 2 4 Load Regulation 0 5 0 4 0 3 0 2 0 1 0 0 1 0 2 0 3 0 4 0 5 0 0 5 1 1 5 2 2 5 3 3 5 Output Voltage Change OUTPUT VOLTAGE vs OUTPUT...

Страница 20: ...ad transients is shown in Figure 2 6 The current step is from 25 to 75 of maximum rated load Total peak to peak voltage variation is as shown including ripple and noise on the output Figure 2 6 Load T...

Страница 21: ...e Figure 2 7 Measured Loop Response TPS54380 VI 3 V 60 50 40 30 20 10 0 10 20 30 40 50 60 100 1 k 10 k 100 k 1 M 180 150 120 90 60 30 0 30 60 90 120 150 180 Gain Phase Gain dB f Frequency Hz MEASURED...

Страница 22: ...oltage ripple is shown in Figure 2 9 The input voltage is 3 3 V for the TPS54380 Output current is the rated full load of 3 A Voltage is measured directly across output capacitors Figure 2 9 Measured...

Страница 23: ...Ripple The TPS54X73EVM 225 output voltage ripple is shown in Figure 2 10 The input voltage is 3 3 V for the TPS54380 Output current for each device is rated full load of 3 A Figure 2 10 Input Voltage...

Страница 24: ...level After that the core regulator starts to regulate its output at the preset 1 8 V level The I O regulator continues its ramp up until the voltage reaches the nominal 3 3 V level The output voltage...

Страница 25: ...ator by using jumper JP2 see schematic in Figure 4 1 If jumper JP2 is set so that R8 is connected in parallel to R7 ratiometric power sequencing is implemented For ratiometric sequencing the following...

Страница 26: ...gure 2 14 Powering Down With Ratiometric Sequencing VO I O 500 mV div Time Scale 1 ms div VO CORE 500 mV div If jumper JP2 is set so that R8 is connected in parallel to R6 the core voltage rises first...

Страница 27: ...nd Results Figure 2 15 Powering Up With Core Voltage Rising First VO I O 500 mV div Time Scale 500 s div VO CORE 500 mV div Figure 2 16 Powering Up With Core Voltage Falling Second VO I O 500 mV div T...

Страница 28: ...2 14...

Страница 29: ...3 1 Board Layout Board Layout This chapter provides a description of the TPS54380EVM 001 board layout and layer illustrations Topic Page 3 1 Layout 3 2 Chapter 3...

Страница 30: ...layer contains ground and VO copper areas and some signal routing The top and bottom ground traces are connected with multiple vias placed around the board including 10 directly under the TPS54380 de...

Страница 31: ...Layout 3 3 Board Layout Figure 3 2 Bottom Side Layout looking from top side...

Страница 32: ...Layout 3 4 Figure 3 3 Top Side Assembly...

Страница 33: ...ematic and Bill of Materials Schematic and Bill of Materials The TPS54380EVM 001 schematic and bill of materials are presented in this chapter Topic Page 4 1 Schematic 4 2 4 2 Bill of Materials 4 3 Ch...

Страница 34: ...C10 0 1 F C5 10 F 1 2 3 4 GND 7 6 5 U1 TPS2013D C11 22 F C17 0 1 F 1 2 J2 VOUT I O GND J3 VOUT CORE GND 1 2 R10 0 C14 0 1 F C13 22 F C12 22 F C2 22 F L1 1 H 2 1 TP3 TP4 TP5 C3 0 047 F R11 2 4 C15 330...

Страница 35: ...270 sq Vishay IHLP 2525CZ 01 1 R1 Resistor chip 10 0 k 1 16 W 1 603 Std Std 1 R2 Resistor chip 9 7 k 1 16 W 1 603 Std Std 1 R3 Resistor chip 6 34 k 1 16 W 1 603 Std Std 1 R4 Resistor chip 71 5 k 1 16...

Страница 36: ...4 4...

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