3.3 Output Voltage Regulation
and
show the load and line regulation for U1.
and
show the load and
line regulation for U2.
Output Current (A)
O
utput Voltage
(
V
)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
1
1.001
1.002
1.003
1.004
1.005
1.006
1.007
1.008
1.009
1.01
V
IN
= 5 V
V
IN
= 12 V
V
IN
= 15 V
Figure 3-6. U1 Load Regulation
Input Voltage (V)
O
utput Voltage (
V)
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
1
1.001
1.002
1.003
1.004
1.005
1.006
1.007
1.008
1.009
1.01
I
OUT
= 0 A
I
OUT
= 3 A
I
OUT
= 6 A
Figure 3-7. U1 Line Regulation
Output Current (A)
O
utput Voltage
(
V
)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0.998
0.999
1
1.001
1.002
1.003
1.004
1.005
1.006
1.007
1.008
V
IN
= 5 V
V
IN
= 12 V
V
IN
= 18 V
Figure 3-8. U2 Load Regulation
Input Voltage (V)
O
utput Voltage (
V)
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
0.998
0.999
1
1.001
1.002
1.003
1.004
1.005
1.006
1.007
1.008
I
OUT
= 0 A
I
OUT
= 3 A
I
OUT
= 6 A
Figure 3-9. U2 Line Regulation
Test Setup and Results
14
TPS543620 SWIFT™ Step-Down Converter Evaluation Module User's Guide
SLVUBQ1A – AUGUST 2020 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated