3.2 Efficiency
through
show the efficiency for both designs on the TPS543620EVM. Using the selection
jumpers for U2, the results for different output voltage and switching frequency combinations are included. The
test points listed in
are used for the efficiency measurement. Use these test points to minimize the
contribution of PCB parasitic power loss to the measured power loss.
The following are some additional test setup considerations to minimize external sources of power dissipation.
• Disable the other regulator to avoid including the switching quiescent current of the other regulator in the
efficiency measurement. When testing U1 with U2 disabled, an external power supply should be used to
power the buffer connected to the FSEL pin as described in
.
• Do not measure the SW pin of U2 with TP28 while measuring the efficiency of U2. Measuring the SW pin with
this test point loads this node with 500 Ω and the efficiency measurement will include the power lost in this
external resistance.
• Remove the shunts from J11 and J13 as a small amount of power is dissipated in the EN resistor divider
connected to U2.
Table 3-3. Efficiency Measurement Test Points
RELATED IC
TEST POINT NAME
REFERENCE
DESIGNATOR
FUNCTION
U1
VIN_U1
TP1
Input voltage test point connected near pins of U1
VOUT_U1
TP2
Output voltage test point near output inductor of U1
PGND_EFF_U1
TP5
PGND reference test point for both input and output
voltages Kelvin connected near U1
U2
VIN_U2
TP12
Input voltage test point connected near pins of U2
VOUT_U2
TP15
Output voltage test point near output inductor of U2
PGND_EFF_U2
TP17
PGND reference test point for both input and output
voltages Kelvin connected near U2
Test Setup and Results
SLVUBQ1A – AUGUST 2020 – REVISED MAY 2021
TPS543620 SWIFT™ Step-Down Converter Evaluation Module User's Guide
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