Texas Instruments TPS54336AEVM-010, Руководство пользователя, Страница: 10 / 20

V = 2 V / div
OUT
Time = 2 msec / div
EN = 5 V / div
V = 20 V / div
IN
SS = 2 V / div
V = 2 V / div
OUT
Time = 2 msec / div
EN = 5 V / div
V = 20 V / div
IN
SS = 2 V / div
Test Setup and Results
www.ti.com
10 SLVUB77 – July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
TPS54336AEVM-010 3-A Regulator Evaluation Module
2.9 Powering Up
Figure 11 and Figure 12 show the start-up waveforms for the TPS54336AEVM-010. In Figure 11 , the
output voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1and
R2 resistor divider network. In
Figure 12 , the input voltage is initially applied and the output is inhibited by
using a jumper at JP1 to tie EN to GND. When the jumper is removed, EN is released. When the EN
voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps
up to the externally set value of 5 V. The input voltage for these plots is 24 V and the load is 5
Ω .
Figure 11. TPS54336AEVM-010 Start-Up Relative to V
IN
Figure 12. TPS54336AEVM-010 Start-up Relative to Enable