Texas Instruments TPS54232EVM-415, Руководство пользователя

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3 Board Layout
This section provides a description of the TPS54232EVM-415, board layout, and layer illustrations.
3.1 Layout
The board layout for the TPS54232EVM-415 is shown in Figure 3-1 through Figure 3-3 . The topside layer of the
EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz. copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. Also on the top layer are connections
for the remaining pins of the TPS54232 and a large area filled with ground. The bottom layer contains ground
and a signal route for the BOOT capacitor. The top and bottom and internal ground traces are connected with
multiple vias placed around the board including ten vias directly under the TPS54232 device to provide a thermal
path from the top-side ground plane to the bottom-side ground plane.
The input decoupling capacitor (C1, C2 is not used) and bootstrap capacitor (C4) are all located as close to the
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC. The
voltage divider network ties to the output voltage at the point of regulation, the copper V
OUT
trace past the output
capacitor (C3, C8 is not used). For the TPS54232, an additional input bulk capacitor may be required, depending
on the EVM connection to the input supply.
Figure 3-1. TPS54232EVM-415 Top-Side Layout
Board Layout www.ti.com
10 TPS54232 Step-Down Converter Evaluation Module User's Guide SLVU277A – JANUARY 2009 – REVISED OCTOBER 2021
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