3.2.1
Modifications of the Bottom Converter
3.2.2
Output Voltage Set Point
Vout
R14 = R15
1
0.8
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ö
´
-
ç
÷
è
ø
(1)
3.2.3
External Clock Synchronization
TPS54160
Rt/Clk
C18
10pF
R11
Rt
R16
49.9 Ω
R17
0 Ω
J9
1
2
TPS54160EVM
3.2.4
Programmable Under Voltage Lock Out and Enable
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Performance Specifications
The bottom converter provides several features that allow custom TPS54160 designs to be evaluated.
Many of the control signals are routed to external connectors for easy access. Additionally, the board uses
0603 or larger components and multiple component footprints to ease soldering and assembly of custom
designs.
To change the output voltage of the EVM, it is necessary to change the value of resistor R14. The value of
R14 can be calculated using
. The converter should be re-compensated if the output voltage is
altered from the factory default
The PWRGD pin of the TPS54160 is pulled up to the output voltage by R4 on the top converter and R12
on the bottom converter. The absolute maximum voltage rating of the PWRGD pin is 6.0V. If the output
voltage of either converter is modified to be above 6.0V, then the corresponding pull up resistor should be
removed so that the absolute maximum rating of the IC is not exceeded.
The EVM supports connection of an external oscillator for the TPS54160 to synchronize too. A zero ohm
resistor should be installed for R17 and a 10pF capacitor installed for C18.
shows the
connections and components to synchronize to an external clock source.
Figure 1. Synchronization to an External Clock
The Under Voltage Lock-out (UVLO) and Enable voltages of the TPS54160 have programmable values as
shown in the datasheet. The UVLO and Enable levels are programmed using R8 and R9 on the EVM. See
the TPS54160 data sheet for how to select the value of these resistors. Capacitor C19 can be installed to
add a delay or noise filtering on the EN pin.
SLVU270 – September 2008
TPS54160EVM-230
5
