Texas Instruments TPS5124EVM-001, Руководство пользователя, Страница: 12 / 23

SLUU182 − March 2004
12 High-Performance Dual Synchronous Buck Conversion Using the TPS5124
4.7 Timer Latch
The TPS5124 includes fault latch function with a user adjustable timer to latch the MOSFET
drivers in case of a fault condition. When either the OVP or UVP comparator detect a fault
condition, the timer starts to charge C18, the external capacitor connected to the SCP pin. The
circuit is designed so that for any value of C18, the undervoltage latch time t
UVPL
is about five
times larger than the overvoltage latch time t
OVPL
. The equations needed to calculate the
required value of C18 for the desired overvoltage and undervoltage latch delay times are
calculated in equations (17) or (18).
C18
+
1.7 10
*
6
t
UVPL
1.185
C18
+
8 10
*
6
t
OVPL
1.185
where
•
C18 is the external capacitor connected to the SCP pin
•
t
UVPL
is the time from UVP detection to latch
•
t
OVPL
is the time from OVP detection to latch
For the EVM, t
UVPL
= 7 ms and t
OVPL
= 1.5 ms, so C18 = 0.01
µ
F.
If the voltage on the SCP pin reaches 1.185 V, the fault latch is set, and the MOSFET drivers are
set as follows:
4.7.1 Undervoltage Protection
The under voltage comparator circuit continually monitors the voltage at the INV pin. If the
voltage at that pin falls below 78% of the 0.85-V reference, the timer begins to charge C18. If the
fault condition persists beyond the time t
UVPL
, the fault latch is set and both the high-side and
low-side drivers is forced OFF.
4.7.2 Short circuit Protection
The short circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the
current limit circuit limits the output current, then the output voltage goes below the target output
voltage and UVP comparator detects a fault condition as described above.
4.7.3 Overvoltage Protection
The over voltage comparator circuit continually monitors the voltage at the INV pin. If V
INV
rises
above 112% of the 0.85-V reference, the timer begins to charge C18. If the fault condition
persists beyond the time t
OVPL
, the fault latch is set and the high-side drivers are forced OFF,
while the low-side drivers are forced ON.
CAUTION:
DO NOT set the SCP terminal to a voltage lower than 1.185 V while the device is
timing out an OVP or UVP event. If the SCP terminal is manually set to a voltage
lower than 1.185 V during this time, output overshoot may occur. The TPS5124
must be reset by grounding STBYx.
(17)
(18)