4 EVM Setup and Operation
This section describes the functionality and operation of the TPS3899EVM. The user should read the TPS3899
data sheet for electrical characteristics of the device.
4.1 Input Power (VDD)
The VDD supply is connected through the J1 header on board. Both pins of jumper J1 are connected together
so power can be applied to either pin. The voltage range is 0.85V to 6V for the open-drain low (DL) and push-
pull low (PL) variations and 1V to 6V for the push-pull high (PH) variations.
4.2 Monitoring Voltage on SENSE Pin
The TPS3899 device monitors voltage via the SENSE pin. The user can connect to the sense pin using TP3.
The EVM provides options for voltage monitoring.
1. Monitor VDD: VDD can be monitored by connecting the shunt to jumper J3 which creates a short and makes
V
MON
= VDD.
2. Voltage divider for V
MON
: V
MON
can connect to SENSE through a voltage divider. To use this voltage divider
connect the shunt to jumper J5 (Rdiv [pin 3] to GND [pin 2]). This voltage divider can be adjusted to monitor
any voltage above the device's V
IT-
for information on the default EVM threshold voltage
values).
Table 4-1. Default EVM Nominal Input Threshold Voltage
V
IT-
V
IT+
V
MON
Negative-Going
Threshold Voltage
V
MON
Positive-Going
Threshold Voltage
TPS3899XX01,
R1 = 47.5k, R2 = 10k
(x0.174 Voltage Divider)
0.51 V
0.536 V
2.93 V
3.08 V
4.3 Reset Output (RESET)
The TPS3899EVM includes the default TPS3899DL01 device variant that includes open-drain, active-low output
topology for the RESET pin. The other device variations provide different output topologies and can be used on
this EVM. If using a TPS3899 device variation with push-pull output topology (PH or PL), the pull-up resistor
must be disconnected by leaving jumper J4 open. It is also possible to apply a separate pull-up voltage by
leaving the jumper J4 open and connecting the pull-up voltage to Vpu [pin 2] of jumper J4. The EVM provides a
jumper J2 and a test point TP2 connected directly to the RESET pin for monitoring and or interfacing to other
devices.
The reset signal is asserted when the voltage on the SENSE pin falls below V
IT-
for the duration of sense delay
time. When the voltage on SENSE rises higher than V
IT+
= V
IT-
+ V
HYS
for the duration of reset delay time, the
reset signal will deassert.
The reset signal will also be asserted when a shunt is connected to jumper J5 (GND [pin 2] to SENSE [pin 1])
which acts as a manual reset.
Please refer to the data sheet for more information on the RESET output and how it reacts to startup conditions
and minimum values of VDD.
EVM Setup and Operation
SLVUBZ3 – SEPTEMBER 2020
TPS3899EVM Voltage Supervisor User Guide
9
Copyright © 2020 Texas Instruments Incorporated
