Texas Instruments TPS2596, Руководство пользователя, Страница: 4 / 20

TP1
VIN1 TP2
VOUT1
TP3
EN1 TP4
FLTb1
GND
1
DVDT
2
EN/UVLO
3
IN
4
OUT
5
FLT
6
ILIM
7
OVCSEL/OVLO
8
GND
9
TPS259621DDAR
U1
TP5
ILIM1
VIN=2.7V-19V
499
R1
200
R2
100k
R3
100k
R10
TP6
OVP1
IIN=0.15A-2A
TP7
DVDT1
1
3
2
NC
D1
Red
D3
J1
1
2
3
4
5
6
J4
330uF
C1
0.1uF
C2
VOUT-1=2.7V-19V
J2
1
2
3
4
5
6
J3
1
2
3
4
5
6
J6
IOUT-1=0.15A-2A
J5
100k
R4
453
R7
82.5k
R9
TP8
GND TP11
GND TP12
GND TP13
GND
NT1
Net-Tie
TP17
VIN2 TP18
VOUT2
TP19
EN2 TP20
FLTb2
GND
1
DVDT
2
EN/UVLO
3
IN
4
OUT
5
FLT
6
ILIM
7
OVCSEL/OVLO
8
GND
9
TPS259630DDAR
U2
TP21
ILIM2
100k
R14
499
R15
200
R16
TP22
OVP2
100k
R13
TP16
DVDT2
Red
D5
VIN=2.7V-19V
1
3
2
NC
D8
J10
J9
1
2
3
4
5
6
J11
IIN=0.15A-2A
VOUT-2=2.7V-19V
330uF
C10
0.1uF
C11
1
2
3
4
5
6
J8
IOUT-2=0.15A-2A
1
2
3
4
5
6
J12 J7
100k
R17
82.5k
R21
453
R22
9.53k
R18
26.7k
R19
46.4k
R20
TP9
GND TP10
GND TP14
GND TP15
GND
NT2
Net-Tie
D2
D6
7.87k
R12
7.87k
R8
FAULT2
FAULT2
FAULT1
FAULT1
VIN1
VIN1
VIN2
VIN2
VOUT2
VOUT1
1uF
C5
1uF
C15
D4
D7
402k
R5 909
R6
909
R11
TP24
SGND2
TP23
SGND1
SGND1
SGND2
0.47uF
C3
0.47uF
C12
0.1uF
C6
0.1uF
C14
S1
S2
0.01uF
C7
0.01uF
C16
0.022uF
C8
0.022uF
C13
0.047µF
C9
0.047µF
C4
DNP
Schematics
www.ti.com
4 SLVUBN7A – April 2019 – Revised August 2019
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Copyright © 2019, Texas Instruments Incorporated
TPS2596EVM: Evaluation Module for TPS2596xx
3 Schematics
Figure 1 illustrates the schematic for this EVM.
Figure 1. TPS2596EVM Schematic
4 General Configurations
This section describes the physical access, test equipment and set up, and the test setup and procedures for this EVM.
4.1 Physical Access
Table 2 lists the TPS2596EVM input and output connector functionality.