Texas Instruments TPS23861EVM-612, Руководство пользователя, Страница: 24 / 39

EVM Schematic, Layout Guidelines and PCB Assembly, Layer Plots
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5.2 Layout Guidelines
5.2.1 Supply Voltage Decoupling
Provide power supply pin bypass to the TPS23861 device as follows:
• 0.1 µF, 100 V, X7R ceramic at pin 28 (VPWR)
• 0.1 µF, 50 V, X7R ceramic at pin 1 (VDD)
5.2.2 Port Current Kelvin Sensing
KSENSA is shared between SEN1 and SEN2, while KSENSB is shared between SEN3 and SEN4. In
order to optimize the accuracy of the measurement, the PCB layout must be done carefully to minimize
the impact of PCB trace resistance. Refer to
Figure 30 as an example.
5.2.3 Ground Plane Spacing and Isolation (GND, GND1, and EARTH nets)
Appropriate spacing should be provided between the GND, GND1, and EARTH nets as shown in
Figure 26 .
5.3 PCB Drawings
Figure 24 through Figure 32 show the PCB layouts and assemblies for this EVM.
Figure 24. TPS23861EVM-612 (Motherboard) Top Side Assembly
24 TPS23861EVM-612: Auto-Mode Evaluation Module for TPS23861 SLUUAY8C – March 2014 – Revised November 2015
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