EVM Assembly Drawings and Layout Guidelines
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12
SLUUBJ1A – February 2017 – Revised June 2017
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Copyright © 2017, Texas Instruments Incorporated
TPS2373-4EVM-758 Evaluation Module
Figure 11. Bottom Component Placement
7.2
Layout Guidelines
The layout of the PoE front end should follow power and EMI and ESD best-practice guidelines. A basic
set of recommendations include:
•
Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer,
diode bridges, TVS and 0.1-
μ
F capacitor, and TPS237x converter input bulk capacitor.
•
Make all leads as short as possible with wide power traces and paired signal and return.
•
No crossovers of signals from one part of the flow to another are allowed.
•
Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input
voltage rails and between the input and an isolated converter output.
•
Place the TPS237x over split, local ground planes referenced to VSS for the PoE input and to
COM/RTN for the converter. Whereas the PoE side may operate without a ground plane, the converter
side must have one. Do not place logic ground and power layers under the Ethernet input or the
primary side of the converter.
•
Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay
copper fills in the power path.
The DC/DC converter layout benefits from basic rules such as:
•
Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses which
include the power semiconductors and magnetics.
•
Minimize trace length of high current, power semiconductors, and magnetic components.
•
Where possible, use vertical pairing.
•
Use the ground plane for the switching currents carefully.
•
Keep the high-current and high-voltage switching away from low-level sensing circuits including those
outside the power supply.
•
Use proper spacing around the high-voltage sections of the converter.