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EVM Assembly Drawing and Layout Guidelines
11
SLVUB75A – August 2017 – Revised September 2017
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Copyright © 2017, Texas Instruments Incorporated
TPS2372-4EVM-006 Evaluation Module
7.2
Layout Guidelines
The layout of the PoE front end should follow power and EMI/ESD best-practice guidelines. A basic set of
recommendations include:
•
Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer,
diode bridges, TVS and 0.1-
μ
F capacitor, and TPS237x converter input bulk capacitor.
•
Make all leads as short as possible with wide power traces and paired signal and return.
•
No crossovers of signals from one part of the flow to another are allowed.
•
Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input
voltage rails and between the input and an isolated converter output.
•
Place the TPS237x over split, local ground planes referenced to VSS for the PoE input and to
COM/RTN for the converter. Whereas the PoE side may operate without a ground plane, the converter
side must have one. Do not place logic ground and power layers under the Ethernet input or the
converter primary side.
•
Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay
copper fills in the power path.