Texas Instruments TPL5010, Руководство пользователя, Страница: 3 / 22

WAKE
Connected
to Q2
J1 J1
Q2 OFF
WAKE
Connected
to IO
J1
RSTn
Connected
to Q1
J1 J1
Q1 OFF
RSTn
Connected
to IO
J1
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Setup
2 Setup
Section 2.1 describes the jumpers and connectors on the EVM and Section 2.3 describes how to properly
connect, set up, and use the TPL5010EVM.
See Figure 1 for locations of the top layer jumpers and switches.
2.1 Jumpers and Connectors
Table 2 through Table 5 list the input/output connectors description, jumpers description, switches and
selectors description, and the test points description.
Table 2. Input/Output Connectors Description
Name Layer Description
J1/J3 Bottom 2 × 10 pin receptacle to plug the TPL5010EVM into the MSP430F5529 LaunchPad
J4/J2 Bottom 2 × 10 pin receptacle to plug the TPL5010EVM into the MSP430F5529 LaunchPad
RST Bottom 2-pin receptacle to plug the TPL5010EVM into the MSP430F5529 LaunchPad
VCC Bottom 2-pin receptacle to plug the TPL5010EVM into the MSP430F5529 LaunchPad
IO Top 4-pin header connector to bring out RSTn, WAKE, DONE, and GND signals
IO.1 GND Ground
IO.2 DONE DONE signal from external microcontroller
IO.3 WAKE WAKE signal to external microcontroller
IO.4 RSTn RSTn signal to external microcontroller
Table 3. Jumpers Description
Name Layer Description
J1 Top J1.5–J1.3 shorted, the RSTn pin of the TPL5010 is connected to the gate of Q1 MOSFET.
J1.3–J1.1 shorted, the gate of Q1 MOSFET is connected to VDD (MOSFET OFF).
Figure 2. J1 Jumper Setting
J1.6–J1.4 shorted, the WAKE pin of the TPL5010 is connected to the gate of Q2 MOSFET.
J1.4–J1.2 shorted, the gate of Q2 MOSFET is connected to VDD (MOSFET OFF).
Figure 3. J1 Jumper Setting
3 SNAU173 – January 2015 TPL5010 Evaluation Module
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