Texas Instruments TPA6120A2RGY EVM, Руководство пользователя

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EVM Circuit and Layout
4 EVM Circuit and Layout
The TPA6120A2RGY EVM layout was carefully planned to minimize the capacitance and inductance
detected by the output and input pins of the amplifier.
This chapter includes the EVM layout, the TPA6120A2RGY EVM component selection, schematic, and
BOM.
4.1 Layout Guidelines
Use the following guidelines during layout:
• Keep layout tight to minimize layout parasitics (that is, keep traces as short as possible and do not
cross signal lines, if possible)
• Maintain symmetry in the layout to maximize common-mode rejection (CMR)
• Maximize copper area connection to the PowerPad for best heat dissipation performance (if cutting the
ground plane, make cuts radially and not circularly)
• Remove ground plane from inputs to minimize stray capacitance
4.2 TPA6120A2RGY EVM PCB Layouts
Figure 2 shows the top copper layer of the TPA6120A2RGY EVM. The RCA jacks at the inputs are
configured to short to ground when no plug is inserted. The noninverting configuration of the EVM requires
that RIN. and LIN. be at ground. Rather than have the signal go through the long signal trace to get to the
input jacks, 0-
Ω resistors R11 and R12 are used to provide a connection to ground much closer to the
device.
A star point for ground should be chosen. For the TPA6120A2RGY EVM, the ground terminal of the board
is (J7). Current paths to the star ground should be as direct as possible.
Figure 3 through Figure 5 illustrate other TPA6120A2RGY EVM copper layers.
Figure 2. TPA6120A2RGY EVM Top Copper Layer Figure 3. TPA6120A2RGY EVM Middle Layer 1
5 SLOU394 – July 2014 TPA6120A2RGY Evaluation Module
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