TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
65
PARAMETER MEASUREMENT INFORMATION
80x8x interrupt acknowledge timing – first SIACK pulse
NO.
PARAMETER
MIN
MAX
UNIT
286
Pulse duration, SIACK high between DIO accesses (see Note 21)
55
ns
287
Pulse duration, SIACK low on first pulse of two pulses
62.5
ns
NOTE 21: The “inactive” chip select is SIACK in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge
cycles.
SIACK
SRD, SWR,
SCS
First
286
287
Second
Figure 30. 80x8x Interrupt Acknowledge Timing – First SIACK Pulse
80x8x interrupt acknowledge timing – second SIACK pulse
NO.
PARAMETER
MIN
MAX
UNIT
255
Delay from SRDY low to SCS high
15
ns
259†
Hold of SAD high-impedance after SIACK low (see Note 21)
0
ns
260
Setup of output data valid before SRDY low
0
ns
261†
Delay from SIACK high to SAD high-impedance (see Note 21)
35
ns
261a
Hold of output data valid after SIACK high (see Note 21)
0
ns
272a
Setup of inactive data strobe high to SIACK no longer high
55
ns
273a
Hold of inactive data strobe high after SIACK high
55
ns
275
Delay from SIACK high to SRDY high (see Note 21)
35
ns
276‡
Delay from SRDY low in the first DIO access to the SIF register to SRDY low in the immediately
following access to the SIF
4000
ns
279†
Delay from SIACK high to SRDY high impedance
65
ns
282a
Delay from SDBEN low to SRDY low in a read cycle
35
ns
282R
Delay from SIACK low to SDBEN low (see
TMS380 Second Generation Token-Ring
User’s Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed
55
ns
283R
Delay from SIACK high to SDBEN high (see Note 21)
35
ns
† This specification is provided as an aid to board design.
‡ This specification has been characterized to meet stated value.
NOTE 21: The “inactive” chip select is SIACK in DIO read and DIO write cycles, and SCS is the “inactive” chip select in interrupt acknowledge
cycles.
