
Sample Rate Generator Clocking Examples
3-15
Sample Rate Generator of the McBSP
SPRU592E
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FSRP/FSXP = 1: Active-low frame-sync pulse
-
RFRLEN1/XFRLEN1 = 11111b: 32 words per frame
-
RWDLEN1/XWDLEN1 = 0: 8 bits per word
-
RPHASE/XPHASE = 0: Single-phase frame and thus (R/X)FRLEN2 and
(R/X)WDLEN2 are ignored
-
RDATDLY/XDATDLY = 0: No data delay
The clock synchronization provided through the GSYNC bit is not supported
on TMS320VC5501 and TMS320VC5502 devices.
3.6.2 Single-Rate ST-Bus Clock
6 is the same as the double-rate ST-bus clock
example in section 3.6.1 except that:
-
CLKGDV = 0: CLKS drives internal CLK(R/X) without any divide down
(single-rate clock).
-
CLKSP = 0: Rising edge of CLKS generates CLKG and internal CLK(R/X)
Figure 3
−
6. Single-Rate Clock Example
WxBy = Word x Bit y
CLKS
(subsequent FSR)
DR, DX
(subsequent FSR)
Internal CLKG, CLKR,
DR, DX (first FSR)
(first FSR)
internal CLKX
Internal CLKG, CLKR,
internal FSX
Internal FSG, FSR,
FSR external
W2B7
W1B1
W1B3
W1B2
W1B4
W1B5
W1B6
W1B0
W1B7
W32B0
W2B7
W1B0
W1B1
W1B2
W1B3
W1B4
W1B5
W1B6
W1B7
ÁÁ
ÁÁ
The rising edge of CLKS is used to detect the external FSR pulse, which is
used to resynchronize internal McBSP clocks and generate a frame-sync
pulse for internal use. The internal frame-sync pulse is generated so that it is
wide enough to be detected on the falling edge of internal clocks.
The clock synchronization provided through the GSYNC bit is not supported
on TMS320VC5501 and TMS320VC5502 devices.
Содержание TMS320VC5509
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