Texas Instruments TMS320VC5509, Справочное руководство

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Clock Generation in the Sample Rate Generator
Sample Rate Generator of the McBSP 3-6 SPRU592E
3.2.2 Choosing a Polarity for the Input Clock
As shown in Figure 3 − 2, when the input clock is received from a pin, you can
choose the polarity of the input clock. The rising edge of CLKSRG generates
CLKG and FSG, but you can determine which edge of the input clock causes
a rising edge on CLKSRG. The polarity options and their effects are described
in Table 3
− 3.
Figure 3 − 2. Possible Inputs to the Sample Rate Generator and the Polarity Bits
CLKSRG
0
1
CLKXP
†
CLKX pin
CLKRP
†
CLKR pin
0
1
CLKSP
§
CLKS pin
§
CLKSM
0
1
SCLKME
To clock dividers
for CLKG and FSG
McBSP internal
input clock
‡
†
On TMS320VC5501 and TMS320VC5502 devices, the polarity of the sample rate generator input clock (CLKSRG) is always
positive (rising edge), regardless of CLKRP or CLKXP.
‡
McBSP internal input clock: On TMS320VC5503/5507/5509 and TMS320VC5510 devices, this clock is the CPU clock. On
TMS320VC5501 and TMS320VC5502 devices, this clock is the slow peripherals clock.
§
Not all C55x devices have a CLKS pin; check the device-specific data manual.