
Sample Rate Generator
Sample Rate Generator of the McBSP
3-2
SPRU592E
3.1 Sample Rate Generator
Each McBSP contains a sample rate generator that can be used to generate
an internal data clock (CLKG) and an internal frame-synchronization signal
(FSG). CLKG can be used for bit shifting on the data receive (DR) pin and/or
the data transmit (DX) pin. FSG can be used to initiate frame transfers on DR
and/or DX. Figure 3
1 is a conceptual block diagram of the sample rate
generator.
Figure 3
−
1. Conceptual Block Diagram of the Sample Rate Generator
FSR
GSYNC
synchronization
¶
and clock
detection
Frame pulse
FWID
CLKG
FSG
Pulse
Frame
FPER
CLKGDV
CLKSRG
÷
÷
0
1
CLKXP
†
CLKX pin
CLKRP
†
CLKR pin
0
1
McBSP internal
CLKSP
§
CLKS pin
§
CLKSM
0
1
SCLKME
input clock
‡
†
On TMS320VC5501 and TMS320VC5502 devices, the polarity of the sample rate generator input clock (CLKSRG) is always
positive (rising edge), regardless of CLKRP or CLKXP.
‡
McBSP internal input clock: On TMS320VC5503/5507/5509 and TMS320VC5510 devices, this clock is the CPU clock. On
TMS320VC5501 and TMS320VC5502 devices, this clock is the slow peripherals clock.
§
Not all C55x devices have a CLKS pin; check the device-specific data manual.
¶
The clock synchronization provided through the GSYNC bit is not supported on TMS320VC5501 and TMS320VC5502 devices.
Содержание TMS320VC5509
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Страница 201: ...Emulation Power and Reset Considerations 10 10 SPRU592E ...
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