
Resetting and Initializing a McBSP
Emulation, Power, and Reset Considerations
10-8
SPRU592E
10.4.4 Resetting the Transmitter While the Receiver is Running
1 shows one case in which the transmitter is reset and configured
while the receiver is running.
Example 10
−
1. Resetting and Configuring the McBSP Transmitter While the
McBSP Receiver Running
SPCR1 = 0001h
SPCR2 = 0030h
; The receiver is running with the receive
; interrupt (RINT) triggered by the
; receiver ready bit (RRDY). The
; transmitter is in its reset state. The
; transmit interrupt (XINT) will be
; triggered by the transmit frame
−
sync
; error bit (XSYNCERR).
PCR = 0900h
; Transmit frame synchronization is
; generated internally according to the
; FSGM bit of SRGR2. The transmit clock
; is driven by an external source. Receive
; frame synchronization continues to be
; driven by an external source. The
; receive clock continues to be driven by
; the sample rate generator. The input
; clock of the sample rate generator is
; supplied by the CLKS pin or by the
; McBSP internal input clock, depending on
; the CLKSM bit of SRGR2.
SRGR1 = 0001h
SRGR2 = 2000h
; The McBSP internal input clock is the
; input clock for the sample rate
; generator. The sample rate generator
; divides the McBSP internal input clock
; by 2 to generate its output clock
; (CLKG). Transmit frame synchronization
; is tied to the automatic copying of data
; from the DXR(s) to the XSR(s).
XCR1 = 0740h
XCR2 = 8321h
; The transmit frame has two phases.
; Phase 1 has eight 16
−
bit words. Phase 2
; has four 12
−
bit words. There is a 1
−
bit
; data delay between the start of a
; frame
−
sync pulse and the first data bit
; transmitted.
SPCR2 = 0031h
; The transmitter is taken out of reset.
Содержание TMS320VC5509
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