
Setting the Transmit Frame-Sync Polarity
Transmitter Configuration
8-24
SPRU592E
8.17 Setting the Transmit Frame-Sync Polarity
19) determines the polarity of the
transmit frame-sync signal.
Figure 8
−
18. Register Bit Used to Set Transmit Frame-Sync Polarity
PCR
15
4
3
2
0
FSXP
R/W-0
Legend:
R = Read; W = Write; -
n
= Value after reset
Table 8
−
19. Register Bit Used to Set Transmit Frame-Sync Polarity
Register
Bit
Name
Function
PCR
3
FSXP
Transmit Frame-Synchronization Polarity
FSXP = 0
Frame-synchronization pulse FSX is active high.
FSXP = 1
Frame-synchronization pulse FSX is active low.
8.17.1 About Frame Sync Pulses, Clock Signals, and Their Polarities
Transmit frame-sync pulses can be either generated internally by the sample
rate generator or driven by an external source. The source of frame sync is
selected by programming the mode bit, FSXM, in PCR. FSX is also affected
by the FSGM bit in SRGR2. Similarly, transmit clocks can be selected to be
inputs or outputs by programming the mode bit, CLKXM, in the PCR.
When FSR and FSX are inputs (FSXM = FSRM= 0, external frame-sync
pulses), the McBSP detects them on the internal falling edge of clock, internal
CLKR, and internal CLKX, respectively. The receive data arriving at the DR pin
is also sampled on the falling edge of internal CLKR. Note that these internal
clock signals are either derived from external source via CLK(R/X) pins or
driven by the sample rate generator clock (CLKG) internal to the McBSP.
When FSR and FSX are outputs, implying that they are driven by the sample
rate generator, they are generated (transition to their active state) on the rising
edge of internal clock, CLK(R/X). Similarly, data on the DX pin is output on the
rising edge of internal CLKX.
Содержание TMS320VC5509
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