Texas Instruments TMS320VC5509, Справочное руководство

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Setting the SRG Input Clock Polarity
7-41 Receiver Configuration SPRU592E
7.24 Setting the SRG Input Clock Polarity
If the signal on the CLKS, CLKX, or CLKR pin is selected as the SRG input
clock, use the CLKSP, CLKXP, or CLKRP bit, respectively, to select the polarity
of the clock. These bits are shown in Figure 7
− 27 and described in Table 7 − 29.
Not all C55x devices have a CLKS pin; check the device-specific data manual.
Note:
On TMS320VC5501 and TMS320VC5502 devices, the polarity of the
SRG input clock is always positive (rising edge), regardless of CLKRP or
CLKXP.
Figure 7 − 27. Register Bits Used to Set the SRG Input Clock Polarity
SRGR2
15 14 13 0
CLKSP
R/W-0
PCR
15 2 1 0
CLKXP CLKRP
R/W-0 R/W-0
Legend: R = Read; W = Write; - n = Value after reset
Table 7 − 29. Register Bits Used to Set the SRG Input Clock Polarity
Register Bit Name Function
SRGR2 14 CLKSP CLKS Pin Polarity
CLKSP determines the input clock polarity when the CLKS pin supplies the
input clock (SCLKME = 0 and CLKSM = 0).
CLKSP = 0 Rising edge on CLKS pin generates CLKG and FSG.
CLKSP = 1 Falling edge on CLKS pin generates CLKG and FSG.
PCR 1 CLKXP CLKX Pin Polarity
CLKXP determines the input clock polarity when the CLKX pin supplies the
input clock (SCLKME = 1 and CLKSM = 1).
CLKXP = 0 Rising edge on CLKX pin generates transitions on CLKG
and FSG.
CLKXP = 1 Falling edge on CLKX pin generates transitions on CLKG
and FSG.