Texas Instruments TMS320TCI648 Series, Руководство пользователя

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Table 2. Branch Metrics for Rate 1/3
Data
Address (hex) MSB LSB
Base BM
3
(t=0) BM
2
(t=0) BM
1
(t=0) BM
0
(t=0)
Base + 4h BM
3
(t=T) BM
2
(t=T) BM
1
(t=T) BM
0
(t=T)
Base + 8h ...
Table 3. Branch Metrics for Rate 1/4
Data
Address (hex) MSB LSB
Base BM
3
(t=0) BM
2
(t=0) BM
1
(t=0) BM
0
(t=0)
Base + 4h BM
7
(t=0) BM
6
(t=0) BM
5
(t=0) BM
4
(t=0)
Base + 8h BM
3
(t=T) BM
2
(t=T) BM
1
(t=T) BM
0
(t=T)
Base + Ch BM
7
(t=T) BM
6
(t=T) BM
5
(t=T) BM
4
(t=T)
Base + 10h ...
The state metric accumulation resolution is 13 bits on the VCP2. Consequently, full 8-bit dynamic range is
available for branch metrics on the TCI648x/9x VCP2, for all constraint lengths and all code rates.
4.2 Soft Input Dynamic Ranges
The VCP2 implementation implies that the soft inputs need to be quantized so that the branch metrics
satisfy the following bound B1 (branch metrics upper bound - absolute value):
2
(C - 1)
- 1 ≥ (2 × (K - 1) + 2) × B
1
K is the constraint length and C determines the truncation of state metrics that can be performed without
loss of decoding performance.
The VCP2 is designed with C = 13. The branch metrics can have a maximum dynamic range of 7 + 1 sign
bits [-128; +127]. This gives another branch metrics upper bound B
2
≤ 128.
So for a given constraint length, min (B
1
, B
2
) gives the final branch metrics maximum bound B.
To satisfy B in the branch metrics calculation, the soft input values, delivered as 8-bit-signed equalized
values, are linearly scaled with the following formula where 1/n is the rate.
Scaled = min (B
1
, B
2
)/n × SoftValue/128
Example
K = 9, then B
1
≤ 227.5 and the branch metrics range B
2
is [-128; +127]. So the branch metrics need to be
in [-128;+127] range.
If rate 1/3, 128/3 42, so the soft inputs need to be scaled by a factor of 0.333333 and saturated within
the range [-42; +42].
Table 4 summarizes the calculations for the different constraint length and rate:
Table 4. VCP2 Soft Inputs Quantization
1/Rate K Scaling Factor Range
2 5, 6, 7, 8, 9 0.5 [-64; +63]
3 5, 6, 7, 8, 9 0.333333 [-42; +42]
4 5, 6, 7, 8, 9 0.25 [-31; +31]
12 TMS320TCI648x/9x Viterbi-Decoder Coprocessor 2 SPRUE09E – May 2006 – Revised December 2009
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