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2.1.2
Clock Configuration
2.1.3
DDR2 Memory Controller Internal Clock Domains
2.2
Memory Map
Peripheral Architecture
The frequency of PLL2_SYSCLK1 is configured by selecting the appropriate PLL multiplier and divider
ratio. The PLL multiplier and divider ratio are selected by programming registers within PLLC2.
Table 1
shows a list of PLL multiplier and divider settings to achieve certain DDR2 frequencies. The data in
Table 1
is derived by assuming a 27-MHZ reference clock. See the device-specific data manual for the
clock frequencies that are supported. See the
TMS320DM643x DMP DSP Subsystem Reference Guide
(
SPRU978
) for information on the PLL controller.
Note:
PLLC2 should be configured and a stable clock present on PLL2_SYSCLK1 before releasing
the DDR2 memory controller from reset.
Table 1. PLLC2 Configuration
PLL Multiplier
PLL Frequency (MHZ)
Divider Ratio
X2_CLK Frequency (MHZ)
DDR2 Clock Frequency (MHZ)
28
756
3
252
126
19
513
2
256.6
128.3
29
783
3
261
130.5
20
540
2
270
135
31
837
3
279
139.5
21
567
2
283.5
141.8
32
864
3
288
144
22
594
2
297
148.5
23
621
2
310
155.3
24
648
2
324
162
25
675
2
337.5
168.8
There are two clock domains within the DDR2 memory controller. The two clock domains are driven by
VCLK and a divided-down by 2 version of X2_CLK called MCLK. The command FIFO, write FIFO, and
read FIFO described in
Section 2.8
are all on the VCLK domain. From this, you can see that VCLK drives
the interface to the peripheral bus.
The MCLK domain consists of the DDR2 memory controller state machine and memory-mapped registers.
This clock domain is clocked at the rate of the external DDR2 memory, X2_CLK/2.
To conserve power within the DDR2 memory controller, VCLK, MCLK, and X2_CLK may be stopped. See
Section 2.16
for proper clock stop procedures.
See the device-specific data manual for information describing the device memory-map.
DDR2 Memory Controller
10
SPRU986B – November 2007
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