Texas Instruments TMS320DM355, Руководство пользователя

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12.1 Overview
12.2 PSC and PLLC Overview
SPRUFB3 – September 2007
Power Management
The DM355 is desigend for minimal power consumption. There are two components to power
consumption: active power and leakage power. Active power is the power consumed to perform work and
scales with clock frequency and the amount of computations being performed. Active power can be
reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to
complete the required operation in the required timeline or to run at a clock setting until the work is
complete and then drastically cut the clocks (e.g. to PLL Bypass mode) until additional work must be
performed. Leakage power is due to static current leakage and occurs regardless of the clock rate.
Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating
junction temperatures. Leakage power can only be avoided by removing power completely from a device
or subsystem.
The DM355 includes several power managment features which are briefly described in Table 12-1 and
detailed in the following sections.
Table 12-1. Power Management Features
Power Management Features Description
Clock Management
Module clock disable Module clocks can be disabled to reduce switching power
Module clock frequency scaling Module clock frequency can be scaled to reduce switching
power
PLL power-down The PLLs can be powered-down when not in use to reduce
switching power
ARM Sleep Mode
ARM Wait-for-Interrupt sleep mode Disable ARM clock to reduce active power
System Sleep Modes
Deep Sleep Mode Stop all device clocks and power down internal oscillators to
reduce active power to a minimum. Registers and memory are
preserved.
Fast NAND Boot Mode (not supported in DM355) Stop all device clocks and power down internal oscillators to
reduce active power to a minimum. Reset and special fast
NAND boot are required to recover from this mode. Memory is
preseved in DDR via auto refresh.
I/O Management
USB Phy power-down The USB Phy can be powered-down to reduce USB I/O power
DAC power-down The DAC's can be powered-down to reduce DAC power
DDR self-refresh and power down The DDR device can be put in self-refresh and power down
states
The power and sleep controller (PSC) plays an important role in managing system power on/off, clock
on/off, and reset. Similarly, the PLL controller (PLLC) plays an important role in device clock generation.
The PSC and the PLLC are mentioned throughout this chapter. For detailed information on the PSC, see
Chapter 7 . For detailed information on the PLLC, see Chapter 5 and Chapter 6 .
SPRUFB3 – September 2007 Power Management 171
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