Texas Instruments TMS320C6A816 Series, Техническое справочное руководство

Страница: 128 / 2034

RAM part CAM part
Virtual address tag N–1 Physical address tag N–1
Virtual address tag 1 Physical address tag 1
Virtual address tag 0 Physical address tag 0
Virtual address tags Physical address tags
Virtual address tag Physical address tag
Preserved bits Endianness Valid bits Element size
Size Mixed bit
P E
P E
P E
V ES
V ES
V ES
S M
S M
S M
0 = nonpreserved
1 = preserved 0 = little endian
1 = big endian 0 = not valid
1 = valid 00 = 8 bit
01 = 16 bit
10 = 32 bit
11 = no conversion 00 = 1MB
01 = 64KB
10 = 4KB
11 = 16MB 0 = use TLB size
1 = use CPU size
Preliminary
System MMU
www.ti.com
Figure 1-23. TLB-Entry Structure
1.4.3.2 MMU Clock Configuration
There are two clock domains: The functional clock domain for the MMU, which is synchronous to the clock
for the interconnect slave and master access ports; and the clock domain for the interconnect slave
configuration port. As these clocks are matched, there is a single input clock with enables for each of the
clock domains. If a clock domain should run at the same frequency as the input clock, that enable can be
tied high.
Two clock enable signals exist, one to enable the interconnect data master and slave ports, and the other
to enable the clock on the configuration L3 interconnect port. The clock signals are configured through the
MMU_SYSCONFIG register. This is a system configuration register that controls the various parameters
of the L3 interface.
1.4.3.3 MMU Software Reset
This section describes the software reset feature of the module. The MMU instances are reset together
with their respective reset domains. See table Clocks and Resets for information about the reset domains
of the different MMU instances.
To perform a software reset, write 1 in the MMU_SYSCONFIG[1] SOFTRESET bit. The
MMU_SYSSTATUS[0] RESETDONE bit indicates that the software reset is complete when its value is 1.
When the software reset completes, the MMU_SYSCONFIG[1] SOFTRESET bit is automatically reset.
The software must ensure that the software reset completes before doing MMU operations. When an
MMU instance is released from reset, its TLB is empty and the MMU is disabled.
1.4.3.4 MMU Power Management
As part of the device system-wide power management scheme, each MMU instance supports a
communication protocol with the PRCM module that allows the PRCM module to request an MMU
instance to enter a low-power state. When the MMU instance acknowledges a low-power mode request
from the PRCM module, the clock to the instance is gated off at the PRCM clock generator. Because the
clock is disabled at the source, the low-power mode offers lower power consumption than the internal
clock gating method in the local power management.
128 Chip Level Resources SPRUGX9 – 15 April 2011
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated