Texas Instruments TMS320C28x, Справочное руководство

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Status Register (ST0)
2-16
2.3 Status Register (ST0)
The following figure shows the bit fields of status register (ST0). All of these
bit fields are modified in the execute phase of the pipeline. Detailed descrip-
tions of these bits follow the figure.
Figure 2 − 10. Bit Fields of Status Register (ST0)
15 10 9 7 6 5 4 3 2 1 0
OVC/OVCU PM V N Z C TC
OVM SXM
R/W-00 0000 R/W − 0 RW−0 RW−0 RW−0 RW−0 RW−0 RW−0 RW−0
ÁÁ
ÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Note: R = Read access; W = Write access; value following dash ( − ) is value after reset.
Á
Á
OVC/OVCU
Bits15 − 10
Overflow counter. The overflow counter behaves differently for signed and unsigned op-
erations.
For signed operations, the overflow counter is a 6-bit signed counter with a range of
− 32
to 31. When overflow mode is off (OVM = 0), ACC overflows normally, and OVC keeps
track of overflows. When overflow mode is on (OVM = 1) and an overflow occurs in ACC,
the OVC is not affected. Instead, the CPU automatically fills ACC with a positive or negative
saturation value (see the description for OVM on page 2-32).
When ACC overflows in the positive direction (from 7FFF FFFF
16
to 8000 0000
16
), the
OVC is incremented by 1. When ACC overflows in the negative direction (from 8000 0000
16
to 7FFF FFFF
16
) the OVC is decremented by 1. The increment or decrement is performed
as the overflow affects the V flag.
For unsigned operations (OVCU), the counter increments for ADD when a Carry is
generated and decrements for a SUB when a Borrow is generated (similar to a carry
counter).
If OVC increments past its most positive value, 31, the counter wraps around to − 32. If OVC
decrements past its most negative value, − 32, the counter wraps around to 31. At reset,
OVC is cleared.
OVC is not affected by overflows in registers other than ACC and is not affected by compare
instructions (CMP and CMPL). The table that follows explains how OVC may be affected
by the saturate accumulator (SAT ACC) instruction.
Table 2 − 4 lists the instructions affecting OVC/OVCU. See the instruction set
in Chapter 6 for a complete description of each instruction.