internally connected to the MCLKR signal, so that both the transmit and receive circuits of the McBSP are
clocked by the external master clock. The FSX pin is also internally connected to the FSR signal, and no
external signal connections are required on the MCLKR and FSR pins.
Although the CLKX signal is generated externally by the master and is asynchronous to the McBSP, the sample
rate generator of the McBSP must be enabled for proper SPI slave operation. The sample rate generator must
be programmed to its maximum rate of half the CPU clock rate. The internal sample rate clock is then used to
synchronize the McBSP logic to the external master clock and slave-enable signals.
The McBSP requires an active edge of the slave-enable signal on the FSX input for each transfer. This means
that the master device must assert the slave-enable signal at the beginning of each transfer, and deassert
the signal after the completion of each packet transfer; the slave-enable signal cannot remain active between
transfers. Unlike the standard SPI, this pin cannot be tied low all the time.
The data delay parameters of the McBSP must be set to 0 for proper SPI slave operation. A value of 1 or 2 is
undefined in the clock stop mode.
15.7 Receiver Configuration
To configure the McBSP receiver, perform the following procedure:
1. Place the McBSP/receiver in reset (see
2. Program McBSP registers for the desired receiver operation (see
3. Take the receiver out of reset (see
).
15.7.1 Programming the McBSP Registers for the Desired Receiver Operation
The following is a list of important tasks to be performed when you are configuring the McBSP receiver. Each
task corresponds to one or more McBSP register bit fields.
• Global behavior:
– Set the receiver pins to operate as McBSP pins.
– Enable/disable the digital loopback mode.
– Enable/disable the clock stop mode.
– Enable/disable the receive multichannel selection mode.
• Data behavior:
– Choose 1 or 2 phases for the receive frame.
– Set the receive word length(s).
– Set the receive frame length.
– Enable/disable the receive frame-synchronization ignore function.
– Set the receive companding mode.
– Set the receive data delay.
– Set the receive sign-extension and justification mode.
– Set the receive interrupt mode.
• Frame-synchronization behavior:
– Set the receive frame-synchronization mode.
– Set the receive frame-synchronization polarity.
– Set the sample rate generator (SRG) frame-synchronization period and pulse width.
• Clock behavior:
– Set the receive clock mode.
– Set the receive clock polarity.
– Set the SRG clock divide-down value.
– Set the SRG clock synchronization mode.
– Set the SRG clock mode (choose an input clock).
– Set the SRG input clock polarity.
Multichannel Buffered Serial Port (McBSP)
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
919
Copyright © 2022 Texas Instruments Incorporated
Содержание TMS320 2806 Series
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