11.9.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)
The source/destination wrap size register is shown in
Figure 11-22. Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE)
15
0
WRAPSIZE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 11-18. Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) Field Descriptions
Bit
Field
Value
Description
15-0
WRAPSIZE
These bits specify the number of bursts to transfer before wrapping back to begin
address pointer:
0x0000
Wrap after 1 burst
0x0001
Wrap after 2 bursts
0x0002
Wrap after 3 bursts
...
...
0xFFFF
Wrap after 65536 bursts
To
disable
the wrap function, set the WRAPSIZE bit field to a number larger than
the TRANSFERSIZE bit field.
11.9.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)
The source/destination wrap count register (SCR/DST_WRAP_COUNT) is shown in
and described
in
.
Figure 11-23. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)
15
0
WRAPCOUNT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 11-19. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) Field Descriptions
Bit
Field
Value
Description
15-0
WRAPCOUNT
These bits indicate the current wrap counter value:
0x0000
Wrap complete
0x0001
1 burst left
0x0002
2 burst left
...
...
0xFFFF
65535 burst left
The above values represent the state of the counter at the HALT conditions.
Direct Memory Access (DMA) Module
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
TMS320x2806x Microcontrollers
755
Copyright © 2022 Texas Instruments Incorporated
Содержание TMS320 2806 Series
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