LEFT
DAC
HPL
HPR
LEFT_DACP
LEFT_DACM
Analog Audio I/O
During the power-down state, the headphone outputs are weakly pulled to ground using an approximately
50k
Ω
resistor to ground, to maintain the output voltage on HPL and HPR pins.
2.2.2.2
Mono Differential DAC to Mono Differential Headphone Output
Figure 2-4. Low Power Mono DAC to Differential Headphone
This configuration supports the routing of the two differential outputs of the mono, left channel DAC to the
headphone amplifiers in differential mode (Page 1 / Register 12, D3 =1 and Page 1 / Register 13, D4 =1).
2.2.2.2.1 Offset Correction Scheme for Differential DAC to Differential Headphone Output
The TLV320DAC3203 offers an offset correction scheme which is based on calibration during power up.
This scheme will minimize differences in DC voltage between the HPL and HPR outputs.
The offset calibration happens after the headphones are powered up in differential mode. All other
headphone configurations like signal routings, gain settings and mute removal needs to be configured
before the power up of headphones. Any change in these settings while the headphones are powered up
may result in additional differential offsets and are best avoided.
The offset calibration block has a few programmable parameters which the user needs to control. The
user can either choose to calibrate the offset at each power-up of headphones or do it only for first power
up of headphone after system power up and hardware reset.
Programming Page 1 / Register 125, D(1:0) as “01” would cause the offset to be calibrated for each power
up of headphone. This is particularly useful when some headphone configurations like gain or signal
routings change between power ups.
Programming Page 1 / Register 125, D(1:0) as “10” would cause the offset to be calibrated for only the
first power-up of the headphone amplifiers after hardware reset. The calibration data will be stored in
internal memory until the next hardware reset or until AVDD power is removed. Since offset calibration is
not done every time the headphone amplifiers power up the turn on time is reduced by approximately 3.6
ms for subsequent powerups.
Programming Page 1 / Reg 125, D (1:0) as “00” (default) will disable offset correction block.
While the offset is being calibrated no signal should be applied to the headphone amplifier, i.e. the DAC
should be kept muted and analog bypass routing should be kept at highest attenuation setting of 78dB.
The user can read Page 1 / Regiseter 2, D2 to poll if calibration is completed (D2=”1” -> calibration is
completed).
Please see
for an example setup script enabling offset correction.
2.2.2.3
Headphone Amplifier Class-D Mode
By default the headphone amplifiers in the TLV320DAC3203 work in Class-AB mode. By writing to Page
1, Register 3, Bits D7-D6) for the left headphone amplifier, and Page 1, Register 4, Bits D7-D6) with value
11, the headphone amplifiers enter a Class-D mode of operation.
In this mode a high frequency digital pulse-train representation of the DAC signal is fed to the load
connected to HPL and HPR outputs.
19
SLAU434 – May 2012
TLV320DAC3203 Application
Copyright © 2012, Texas Instruments Incorporated
