Texas Instruments TLC694 Series, Техническое справочное руководство

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LOD Data Register
LOD Bit 15 LOD Bit 14 LOD Bit 13 LOD Bit 12 LOD Bit 2 LOD Bit 3 LOD Bit 1 LOD Bit 0
Channel 15 Channel 14 Channel 13 Channel 12 Channel 3 Channel 2 Channel 1 Channel 0
MSB LSB
«
OUT0
+
±
LODVTH
Channel
Control
OUT1
+
±
LODVTH
16-bit LOD Data
16-bit Common Shift Register
MSB LSB
SIN
SOUT
SCLK
16-bit READLOD
GND
GND
LED Open Detection
0: Normal
1: LED Open
Channel
Control
OUT1
+
±
LODVTH
Channel
Control
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Function-Control Description
21 SLVUBF4A – February 2018 – Revised June 2019
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Function Control
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2.3.2 LED Open Detection (LOD)
2.3.2.1 LOD Overview
The LED-open detection (LOD) function detects faults caused by an open circuit in any LED string, or a
short from OUTn to ground with low impedance. It does this by comparing the OUTn voltage to the LOD-
detection threshold-voltage level set by LODVTH in the function-control register 1 (see FC1 in
Table 2-2 ).
If the OUTn voltage is lower than the programmed voltage, the corresponding output LOD bit is set to 1 to
indicate an open LED. Otherwise, the output of that LOD bit is 0. LOD data output by the detection circuit
are valid only during the on-period of that OUTn output channel. The LOD data are always 0 for outputs
that are turned off.
Figure 2-14 shows the equivalent circuit of LED open detection.
Figure 2-14. LED Open-Detection Circuit
The LED open-detection result is latched into the internal 16-bit LOD data register at the rising edge of the
last second GCLK in each segment.
Figure 2-15 shows the bit arrangement of the LOD data register.
Figure 2-15. Bit Arrangement in the LOD Data Register
2.3.2.2 Read LOD Information
The TLC694x device treats 13 SCLK rising edges during the LAT signal-high period as a read-LOD-
information (READLOD) command (
Table 2-13 ). Once this command is received, the 16-bit data in the
LOD data holder (register) are latched into the common shift register at the falling edge of the LAT signal.
After that, input 16 SCLK rising edges to shift out the LOD data at the SOUT pin.
Figure 2-16 shows the
timing diagram of the read-LOD-information operation.