Texas Instruments TLC694 Series, Техническое справочное руководство

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SIN
SCLK
SOUT
16-bit
This data latch pulse is generated when
the WRTFC command is received.
16-bit
Common Shift Register
Function Control Registers
Grayscale (GS) Memory Units
16-bit
This data latch pulse is generated when the WRTGS command is
received. Memory unit is selected by internal counters.
GS Bit 15 GS Bit 14 GS Bit 13 GS Bit 12 GS Bit 2 GS Bit 3 GS Bit 1 GS Bit 0
MSB LSB
«
FC4 Bit 15 FC4 Bit 14 FC4 Bit 13 FC4 Bit 12 FC4 Bit 2 FC4 Bit 3 FC4 Bit 1 FC4 Bit 0
MSB LSB
«
FC4
FC3 Bit 15 FC3 Bit 14 FC3 Bit 13 FC3 Bit 12 FC3 Bit 2 FC3 Bit 3 FC3 Bit 1 FC3 Bit 0
MSB LSB
«
FC3
FC2 Bit 15 FC2 Bit 14 FC2 Bit 13 FC2 Bit 12 FC2 Bit 2 FC2 Bit 3 FC2 Bit 1 FC2 Bit 0
MSB LSB
«
FC2
FC1 Bit 15 FC1 Bit 14 FC1 Bit 13 FC1 Bit 12 FC1 Bit 2 FC1 Bit 3 FC1 Bit 1 FC1 Bit 0
MSB LSB
«
FC1
Common Data
Bit 15
Common Data
Bit 14
Common Data
Bit 13
Common Data
Bit 12
Common Data
Bit 2
Common Data
Bit 3
Common Data
Bit 1
Common Data
Bit 0
MSB LSB
«
Common Shift Register
10 SLVUBF4A – February 2018 – Revised June 2019
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Function Control
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Chapter 2
SLVUBF4A – February 2018 – Revised June 2019
Function Control
2.1 Function-Control Registers
Function-control registers are used to store the configuration information which controls the TLC694x
operating mode. There are four function-control register groups integrated in the TLC694x device, FC1,
FC2, FC3, and FC4. The following sections give detailed description of each function-control register
group, and how to write function-control data into each function-control register group.
2.1.1 Write Function-Control Data Through a Common Shift Register
The common shift register is 16 bits long and is used to shift data from the SIN pin into the TLC694x
device. The data shifted into the register can be latched into the grayscale (GS) memory unit or latched
into the function-control (FC) registers, depending on the command received.
Figure 2-1 shows the configuration of the common shift register and the data latches.
Figure 2-1. Common Shift Register and Data Latch Configuration