Texas Instruments TL16C750EEVM, Руководство пользователя

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5 V Processor to 3.3 V V
CC
on TL16C750E
3 SLLU317 – January 2020
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TL16C750EEVM User's Guide
2x8 male headers are provided to connect between a processor and the EVM for the level translation.
Header denoted as J2 allows for the bidirectional data pins (D0-D7) to be accessed. The 5 V input pins
RESET, A0, A1, A2, CS, IOW, and IOR can be accessed at J22. The INT, TXRDY, and RXRDY lines
each have their own 1x1 headers denoted as J6, J8, and J17 respectively. The 5 V inputs RI, CD, DSR,
CTS, and RX can be found at J23. The 5 V outputs DTR, RTS, OP, and TX can be located at J20.The 5V
interfacing headers are highlighted in
Figure 2 .
Figure 2. 5.5 V to 3.3 V interface image