System Control
ROM Location:
ROM_APITABLE
is an array of pointers located at
0x0100.0010
.
ROM_SYSCTLTABLE
is an array of pointers located at
ROM_APITABLE[13]
.
ROM_SysCtlClockGet
is a function pointer located at
ROM_SYSCTLTABLE[24]
.
Description:
This function determines the clock rate of the processor clock. This is also the clock rate of all
the peripheral modules (with the exception of PWM, which has its own clock divider).
Note:
This will not return accurate results if
has not been called to configure
the clocking of the device, or if the device is directly clocked from a crystal (or a clock source)
that is not one of the supported crystal frequencies. In the later case, this function should be
modified to directly return the correct system clock rate.
Returns:
The processor clock rate.
18.2.1.4 ROM_SysCtlClockSet
Sets the clocking of the device.
Prototype:
void
ROM_SysCtlClockSet(uint32_t ui32Config)
ROM Location:
ROM_APITABLE
is an array of pointers located at
0x0100.0010
.
ROM_SYSCTLTABLE
is an array of pointers located at
ROM_APITABLE[13]
.
ROM_SysCtlClockSet
is a function pointer located at
ROM_SYSCTLTABLE[23]
.
Parameters:
ui32Config
is the required configuration of the device clocking.
Description:
This function configures the clocking of the device. The input crystal frequency, oscillator to be
used, use of the PLL, and the system clock divider are all configured with this function.
The
ui32Config
parameter is the logical OR of several different values, many of which are
grouped into sets where only one can be chosen.
The system clock divider is chosen with one of the following values:
SYSCTL_SYSDIV_1
,
SYSCTL_SYSDIV_2
,
SYSCTL_SYSDIV_3
, ...
SYSCTL_SYSDIV_64
.
The use of the PLL is chosen with either
SYSCTL_USE_PLL
or
SYSCTL_USE_OSC
.
The
external
crystal
frequency
is
chosen
with
one
of
the
following
val-
ues:
SYSCTL_XTAL_1MHZ
,
SYSCTL_XTAL_1_84MHZ
,
SYSCTL_XTAL_2MHZ
,
SYSCTL_XTAL_2_45MHZ
,
SYSCTL_XTAL_3_57MHZ
,
SYSCTL_XTAL_3_68MHZ
,
SYSCTL_XTAL_4MHZ
,
SYSCTL_XTAL_4_09MHZ
,
SYSCTL_XTAL_4_91MHZ
,
SYSCTL_XTAL_5MHZ
,
SYSCTL_XTAL_5_12MHZ
,
SYSCTL_XTAL_6MHZ
,
SYSCTL_XTAL_6_14MHZ
,
SYSCTL_XTAL_7_37MHZ
,
SYSCTL_XTAL_8MHZ
,
SYSCTL_XTAL_8_19MHZ
,
SYSCTL_XTAL_10MHZ
,
SYSCTL_XTAL_12MHZ
,
SYSCTL_XTAL_12_2MHZ
,
SYSCTL_XTAL_13_5MHZ
,
SYSCTL_XTAL_14_3MHZ
,
200
April 8, 2013
Содержание Tiva TM4C123GH6PM
Страница 26: ...Boot Loader 26 April 8 2013...
Страница 68: ...Controller Area Network CAN 68 April 8 2013...
Страница 122: ...Hibernation Module 122 April 8 2013...
Страница 136: ...Inter Integrated Circuit I2C 136 April 8 2013...
Страница 152: ...Memory Protection Unit MPU 152 April 8 2013...
Страница 174: ...Pulse Width Modulator PWM Returns None 174 April 8 2013...
Страница 196: ...Synchronous Serial Interface SSI 196 April 8 2013...
Страница 222: ...System Control 222 April 8 2013...
Страница 270: ...UART 270 April 8 2013...
Страница 296: ...uDMA Controller 296 April 8 2013...
Страница 351: ...April 8 2013 351...