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2–6

2.5

Operating Characteristics Over Full Range of Operating Conditions
(Unless Otherwise Noted)

2.5.1

Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.125 V peak-to-peak,

0 kHz to 8 kHz (see Note 4)

0.5

0.75

0.125 V peak-to-peak,

8 kHz to 15 kHz (see Note 5)

Frequency

0.125 V peak-to-peak,

16.2 kHz to 18 kHz (see Note 5)

– 26

response

0.125 V peak-to-peak,

18 kHz to 45 kHz (see Note 5)

– 30

0.125 V peak-to-peak,

45 kHz to 75 kHz (see Note 5)

– 46

0.125 V peak-to-peak,

> 75 kHz

– 60

Peak-to-peak
group delay
distortion

0.125 V peak-to-peak,

0 kHz to 15 kHz

Absolute channel
delay, RXI, Q IN to
digital OUT

0.125 V peak-to-peak,

0 kHz to 15 kHz

325

NOTES:

4. Deviation from ideal 0.35 square-root raised-cosine (SQRC) response
5. Stopband

2.5.2

Receive (RX) Channel Frequency Response (FM Input in Analog Mode)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2.5 V peak-to-peak,

0 kHz to 6 kHz (see Note 6)

0.5

Frequency response

2.5 V peak-to-peak,

20 kHz to 30 kHz (see Note 5)

– 18

2.5 V peak-to-peak,

34 kHz to 46 kHz (see Note 7)

– 48

Peak-to-peak group
delay distortion

2.5 V peak-to-peak,

0 kHz to 6 kHz

Absolute channel delay

2.5 V peak-to-peak,

0 kHz to 6 kHz

400

NOTES:

5. Stopband
6. Ripple magnitude
7. Stopband and multiples of stopband

2.5.3

Transmit (TX) Channel Frequency Response (Digital Mode)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0 kHz to 8 kHz (see Note 4)

0.3

8 kHz to 15 kHz (see Note 4)

0.5

Frequency response

20 kHz to 45 kHz (see Note 5)

– 29

Frequency response

45 kHz to 75 kHz (see Note 5)

– 55

> 75 kHz (see Note 5)

– 60

Any 30 kHz band centered at > 90 kHz (see Note 5)

– 60

Peak-to-peak group
delay distortion

0 kHz to 15 kHz

Absolute channel delay

0 kHz to 15 kHz

320

NOTES:

4. Deviation from ideal 0.35 square-root raised-cosine (SQRC) response
5. Stopband

Содержание TCM4300

Страница 1: ...Data Manual 1996 Mixed Signal Products...

Страница 2: ...Printed in U S A 10 96 SLWS010F...

Страница 3: ...TCM4300 Data Manual Advanced RF Cellular Telephone Interface Circuit ARCTIC SLWS010F October 1996 Printed on Recycled Paper...

Страница 4: ...ED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to...

Страница 5: ...stics Over Full Range of Operating Conditions 2 6 2 5 1 Receive RX Channel Frequency Response RXI RXQ Input in Digital Mode 2 6 2 5 2 Receive RX Channel Frequency Response FM Input in Analog Mode 2 6...

Страница 6: ...eneration 4 12 4 11 2 Speech Codec Clock Generation 4 12 4 11 3 Microcontroller Clock 4 12 4 11 4 Sample Interrupt SINT 4 12 4 11 5 Phase Adjustment Strategy 4 13 4 12 Frequency Synthesizer Interface...

Страница 7: ...ite Cycle MTS 1 0 10 3 7 3 8 Microcontroller Interface Timing Requirements Motorola 8 Bit Read Cycle MTS 1 0 01 3 8 3 9 Microcontroller Interface Timing Requirements Motorola 8 Bit Write Cycle MTS 1 0...

Страница 8: ...lope AGC AFC PWRCONT 4 10 4 12 Auxiliary D A Converters Slope LCDCONTR 4 11 4 13 RSSI Battery A D Converter 4 11 4 14 Synthesizer Control Fields 4 17 4 15 External Power Control Signals 4 18 4 16 Micr...

Страница 9: ...thesizer interface circuit The TCM4300 provides advanced power control to minimize the power consumption of many dual mode telephone functional blocks such as the speech codec FM receiver I and Q demo...

Страница 10: ...TX Data Registers TXQ 05b TX Offset Anti aliasing Filter Digital Filter Analog Mode LPF Digital Mode SQRC Sample Register RXI 02h RXQ 03h DSP Interface Data Control Address Anti aliasing Filter Low P...

Страница 11: ...MCLKIN MCCLK RSOUTL RSINL MCD7 MCD5 MCD4 MCD3 MCD2 MCD1 MCD0 BAT FM RXQN RXQP RXIN RXIP AFC VHR VCM PWRCONT TXIP TXIN TXQP TXQN TXEN TXONIND PAEN REFCAP RBIAS IQRXEN FMRXEN SCEN CSCLK CMCLK DSPD9 DSP...

Страница 12: ...low signal that is sent to the DSP CINT is caused by a microcontroller write to the Send C interrupt register location CMCLK 92 O Codec master clock CMCLK provides a 2 048 MHz clock that is used as t...

Страница 13: ...O Liquid crystal display LCD contrast This LCDCONTR control DAC can be used to control the amount of drive to the liquid crystal display MCLKOUT 67 O Master clock out MCLKOUT is a buffered version of...

Страница 14: ...EN 25 O Power amplifier enable PAEN can be used to enable the transmit power amplifier This signal is active high PWRCONT 16 O Power amplifier PA power control The PWRCONT DAC output can be used to co...

Страница 15: ...hase differential negative baseband transmit The negative component of the differential baseband transmit signal is output from TXIN TXIP 17 O In phase differential positive baseband transmit The posi...

Страница 16: ...dissipation See Dissipation Rating Table Operating free air temperature range TA 40 C to 85 C Storage temperature range Tstg 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 26...

Страница 17: ...mption PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog transmitting and receiving DVDD 3 V AVDD 3 V 65 75 mW Analog transmitting and receiving DVDD 5 5 V AVDD 5 5 V 250 275 mW Digital receiving DVDD...

Страница 18: ...le ended 0 5 Vp p Nominal operating Differential 0 125 Vp p Nominal operating level Single ended 0 125 Vp p Input CMRR RXI RXQ 45 dB Sampling frequency SINT digital mode 48 6 kHz Sampling frequency SI...

Страница 19: ...hannel differential or single ended 10 mV Load impedance between P and N terminals 10 k Transmit offset DACs I and Q resolution 6 bits Transmit offset DACs I and Q average step size 2 9 3 4 3 9 mV Tra...

Страница 20: ...CONTR AUXFS 1 0 SETTING SLOPE NOMINAL LSB VALUE V NOMINAL OUTPUT VOLT AGE FOR DIGITAL CODE 8 MIDRANGE V NOMINAL OUTPUT VOLTAGE FOR DIGITAL CODE 16 MAX VALUE V 00 2 5 16 0 1563 1 25 2 5 01 Do not use D...

Страница 21: ...hannel Frequency Response FM Input in Analog Mode PARAMETER TEST CONDITIONS MIN TYP MAX UNIT F 2 5 V peak to peak 0 kHz to 6 kHz see Note 6 0 5 dB Frequency response 2 5 V peak to peak 20 kHz to 30 kH...

Страница 22: ...Hz to 15 kHz see Note 4 0 5 dB Frequency response 20 kHz to 45 kHz see Note 5 31 dB Frequency response 45 kHz to 75 kHz see Note 5 70 dB 75 kHz see Note 5 70 Any 30 kHz band centered at 90 kHz see Not...

Страница 23: ...2 8...

Страница 24: ...gh 3 11 All parameters shown in the separate waveforms have their values listed in an associated table Not all parameter values listed in the tables are necessarily shown in an associated waveform 3 1...

Страница 25: ...n falling edge of strobe MCDS to valid data MCD TRD DV 50 ns tinv Data MCD invalid after rising edge of strobe MCDS TRD INV 10 ns tdis RD Disable time read data TCM4300 releases MCD data bus after ris...

Страница 26: ...trobe MCDS TWD SU 14 ns th W Hold time write data stable MCD after rising edge of strobe MCDS TWD HO 0 ns tw WSTB Pulse duration write strobe pulse width low on MCDS TWR STB 60 ns th CS Hold time chip...

Страница 27: ...s tinv Data MCD invalid after rising edge of strobe MCDS TRD INV 10 ns tdis RD Disable time read data TCM4300 releases MCD data bus after rising edge of strobe MCDS TRD DIS 28 ns tsu CS Setup time chi...

Страница 28: ...after rising edge of strobe MCRW TWD HO 0 ns tw WSTB Pulse duration write strobe pulse width low on MCRW TWR STB 60 ns tsu CS Setup time chip select MCCSH and MCCSL stable before falling edge of strob...

Страница 29: ...d data on falling edge of strobe MCDS to valid data MCD TRD DV 50 ns tinv Data MCD invalid after rising edge of strobe MCDS TRD INV 10 ns tdis RD Disable time read data TCM4300 releases MCD data bus a...

Страница 30: ...e of strobe MCDS TWD SU 14 ns th W Hold time write data stable MCD after rising edge of strobe MCDS TWD HO 0 ns tw WSTB Pulse duration write strobe pulse width low on MCDS TWR STB 60 ns th CS Hold tim...

Страница 31: ...data on rising edge of strobe MCDS to valid data MCD TRD DV 50 ns tinv Data MCD invalid after falling edge of strobe MCDS TRD INV 10 ns tdis RD Disable time read data TCM4300 releases MDS data bus af...

Страница 32: ...of strobe MCDS TWD SU 14 ns th W Hold time write data stable MCD after falling edge of strobe MCDS TWD HO 0 ns tw WSTB Pulse duration write strobe pulse width high on MCDS TWR STB 60 ns th CS Hold ti...

Страница 33: ...address DSPA stable before strobe DSPSTRBL goes low TWA SU 0 ns th RA Hold time read address DSPA stable after strobe DSPSTRBL goes high TWA HO 0 ns ten R Enable time read data on falling edge of stro...

Страница 34: ...after rising edge of strobe DSPSTRBL TCS HO 0 ns tsu WA Setup time write address DSPA stable before falling edge of strobe DSPSTRBL TWA SU 0 ns th WA Hold time write address DSPA stable after rising...

Страница 35: ...3 12...

Страница 36: ...s well To save power the receive I and Q channels are enabled separately This operation occurs because in the analog mode only the Q channel is used When the FMVOX bit is set to 1 it controls the inpu...

Страница 37: ...V FM input sensitivity for full scale 14 kHz deviation 2 5 Vp p FM input dc offset wrt VHR 80 mV FM input idle channel noise below full scale input 50 dB FM gain error 6 Power supply rejection f 0 kHz...

Страница 38: ...delay distortion 0 125 V peak to peak 0 kHz to 15 kHz 2 s Absolute channel delay RXI Q IN to digital OUT 0 125 V peak to peak 0 kHz to 15 kHz 325 s NOTES 2 Stopband 4 Deviation from ideal 0 35 square...

Страница 39: ...put level constellation radius centered at Differential 1 5 V Nominal output level constellation radius centered at VCM Single ended 0 75 V Low level drift 200 PPM C Transmit error vector magnitude EV...

Страница 40: ...DStatCtrl register The SINT interrupt output interrupts the DSP at 48 6 kHz which is T 2 interval T 1 symbol period 1 24 3 kHz The burst is initiated by the DSP writing 1 to 5 dibits to the TXI regis...

Страница 41: ...s of 1 4 SINT 1 8 symbol period For delays of 1 SINT or greater the fractional part of the delay can be achieved using the BST offset register with the remaining integer SINT delay implemented externa...

Страница 42: ...300 other than the fixed ramping In the analog mode the output of the TCM4300 depends only on the sample values written to the TXI and TXQ registers There are small differences in the average output p...

Страница 43: ...r may momentarily lock to the wrong edge because it cannot distinguish the midpoint edges from the data edges A small number of additional bits may be lost in this instance When the WBD_LCKD bit is se...

Страница 44: ...BD stream carries with it a 10 kHz clock The Manchester coded data format contains a transition at the middle of every bit clock period which aids in clock recovery The polarity of the transition is d...

Страница 45: ...nverter is a separate 4 bit DAC The auxiliary DACs can be powered down The AGC and AFC DACs have dedicated bits in the MIntCtrl register to enable the DACs The PWRCONT DAC is enabled by the TXEN bit i...

Страница 46: ...latest RSSI or battery voltage A D conversion has been completed and can be read from the RSSI or BAT register location CVRDY clears to 0 when the microcontroller reads either of these locations Table...

Страница 47: ...requency of MCLKIN is therefore MCLKIN 63 19 1 18 64 2 048092 MHz CSCLK is exactly CMCLK divided by 256 see Figure 4 4 To save power the codec clocks are only generated by TCM4300 when the SCEN bit of...

Страница 48: ...d for the duration of the timing adjustment resulting in a timing delay If a positive number is written the clock periods are shortened for the duration of the timing adjustment resulting in a timing...

Страница 49: ...lock 303 75 kHz WBD Demod 6 48 MHz ADC Clocks DAC Clocks N 5 10 N 2 3 32 Sync Enable Logic MCLKEN From Micro controller 38 88 MHz MCLKIN From DSP Microcontroller Clock MCCLK External Clock Output MCLK...

Страница 50: ...provided There is one for each synthesizer chip The attributes of this interface are controlled by means of the synthesizer control registers SynCtrl0 SynCtrl1 and SynCtrl2 These attributes determine...

Страница 51: ...CNT 0 31 M U X 32 32 Bit Data Register 8 Control Registers 5 5 5 3 Ready and Timing Logic SYNRDY To MStatCtrl Register CLKPOL NUMCLKS LOWVAL HIGHVAL SEL 2 0 MSB LSB FIRST SYNDTA SYNLE0 SYNLE1 SYNLE2...

Страница 52: ...interface is defined to occur at bit time 0 independent of any MSB LSB selection MSB LSB FIRST Writing a 0 to MSB LSB FIRST causes the LSB SynData0 0 to be the first bit sent to SYNDTA of the serial s...

Страница 53: ...ol Port For systems requiring minimum system current consumption power can be provided to each functional part of the TCM4300 only when that function is required for proper system operation To accompl...

Страница 54: ...de is used in analog mode The FMVOX bit controls the Q side input multiplexer When FMVOX is high the QP side of the receiver is connected to the FM input terminal the QN input is connected to the VHR...

Страница 55: ...FIFO B Send DINT DINT Status Clear CINT DSP C 8 8 DINT CINT Figure 4 10 Microcontroller DSP Data Buffers To send data to the DSP the microcontroller writes data to FIFO A To indicate to the DSP that...

Страница 56: ...r to DSP DSP to microcontroller LSB 02h MIntCtrl Clear WBD Clear F Clear D Send C AGCEN AFCEN FMRXEN Reserved 03h SynData0 MSB LSB 04h SynData1 MSB LSB 05h SynData2 MSB LSB 06h SynData3 MSB LSB 07h Sy...

Страница 57: ...Miscellaneous status control R W 0Fh TXI Offset Transmit dc offset compensation W 10h TXQ Offset Transmit dc offset compensation W 4 16 Wide Band Data Control Register This register is used for two f...

Страница 58: ...i 2 through 32 are valid 0 1 moduli are prohibited The clock speed change occurs after the write is complete MIntCtrl Bits 7 4 The bit names in this field indicate the resulting action when the bit is...

Страница 59: ...SI or battery voltage A D conversion is complete and can be read from the RSSI or battery register location CVRDY goes to 0 when the microcontroller reads from either of these locations 1 2 R W AuxFS...

Страница 60: ...rved 08h Timing Adj MSB LSB 09h AGC DAC MSB LSB Reserved 0Ah AFC DAC MSB LSB Reserved 0Bh PWR DAC MSB LSB Reserved 0Ch DStatCtrl TXGO MODE SCEN FMVOX FMRXEN IQRXEN TXEN OUT1 RXOF ALB 0Dh BST Offset Re...

Страница 61: ...recently received bit as shown below WBD 9 2 1 0 WBD WB Data Reserved R WBDC l 9 8 7 5 4 0 WBDCtrl WBD_LCKD WBD_ON WBD_BW Reserved R W 4 21 Base Station Offset Register BST OFFSET values are 00 01 10...

Страница 62: ...modes of operation and the Q side filter 0 7 R W SCEN Speech codec enable microphone speaker interface chip SCEN is connected to bits SCEN also enables 1 or disables 0 the internal speech codec clock...

Страница 63: ...arity requirements of any external device The TCM4300 internal registers are reset when the POR outputs are activated See Figure 4 12 tw 10 ms Minimum 90 10 90 10 DVDD RSOUTH RSOUTL Figure 4 12 Power...

Страница 64: ...asserted when MCCSH 1 and MCCSL 0 4 24 1 Intel Microcontroller Mode Of Operation When the microcontroller type select inputs MTS1 and MTS0 are both held low the TCM4300 micro controller interface is c...

Страница 65: ...e TCM4300 microcontroller interface is configured for 8 bit family 6800 family derivatives e g 68HC11D3 and 68HC11G5 bus characteristics and when the microcontroller selects MTS0 low and MTS1 high the...

Страница 66: ...68000 68008 CS1 CS2 or CS3 68302 MCD7 MCD0 D 7 0 data bus on microcontroller MCA4 MCA0 A 4 0 68008 A 5 1 68000 68302 MCRW R W MCDS DS active low data strobe 68008 LDS active low data strobe 68000 6830...

Страница 67: ...4 32...

Страница 68: ...NOM Gage Plane 0 25 0 45 0 75 0 05 MIN 0 27 51 25 75 1 12 00 TYP 0 17 76 100 SQ SQ 15 80 16 20 13 80 1 35 1 45 1 60 MAX 14 20 0 7 Seating Plane 0 08 0 50 M 0 08 NOTES A All linear dimensions are in m...

Страница 69: ...ED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to...

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