TAS54x4C Hardware Design Guidelines
1.7.1
Understanding Load Diagnostics Timing
Load diagnostics consists of four testing phases and two non-testing phases.
lists the duration of
the tests. Changing the values bit 3 and 4 in register 0x10 changes the duration of the tests or adds a
pause between the S2P test and the OL test.
The need for the longer duration allows for larger common mode capacitors in the output filter. To prevent
false or inconsistent short indications the total capacitance on each output pin to ground for the S2G and
S2P should not exceed 680 nF.
Table 3. Load Diagnostic Timing
PHASE
DEFAULT SETTINGS (ms)
EXTENDED TIME SETTING (ms)
LDP SETTING (ms)
Sync
20
20
20
S2G
20
80
20
S2P
20
80
20
LDP
0
0
20
OL
150
150
150
SL
250
250
250
The first phase is the sync phase. This time allows the channels to synchronize the test sequence before
the test begins. The next two phases test the 8 output terminals for shorts to ground or power. Both
outputs are pulled to the PVDD pin or ground with current sources and not the power FETs. A short to
ground failure occurs if any output does not reach either PVDD pin. Likewise, if any output does not reach
the ground, a short-to-power failure occurs. If a boosted PVDD is used, the S2P test can still detect a
short to battery. The OL and SL tests derive the signal by charging and discharging the MUTE capacitor.
This signal is directed to the output pins. The signal is measured differentially across the two outputs pins
of the channel. If the correct amplitude is not measure either a SL or OL fault is created.
Any faults determined during the load diagnostic will be displayed in I
2
C registers 0x02 and 0x03. These
values persist in the registers until a new load diagnostic is performed or a reset is performed.
Figure 7. Load-Diagnostic Output-Waveforms Timing Diagram
NOTE:
Note that these waveforms are presented in this form to emphasize how the load diagnostic
signal is being applied by the device. The actual amplitude of the applied signals in Phase 3
(open load) and in Phase 4 (shorted load) are highly load dependent, and may have a
greatly decreased amplitude compared to those shown in
when a load is properly
connected.
14
TAS54x4C Design Guide
SLOA196 – June 2014
Copyright © 2014, Texas Instruments Incorporated
