Texas Instruments TAS3208EVM-LC, Руководство пользователя

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3.1 Digital Audio Interface
3.1.1 Digital Input Header
3.1.2 Digital Output Header
Digital Audio Interface
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The digital audio interface contains the digital I
2
S clocks and data. Please refer to the TAS3208 Data
Manual for signal timing an overview of the I
2
S protocol.
Table 3-1. Digital Audio Input Interface (J1)
HEADER
SIGNAL NAME SCHEMATIC NET NAME
PIN ASSIGNMENT
Master clock input MCLKIN 1
Digital ground GND 2
Serial clock input SCLKIN 3
Digital ground GND 4
Left/right clock input LRCLKIN 5
Digital ground GND 6
Serial data 1 input SDIN1 7
Digital ground GND 8
Serial data 2 input SDIN2 9
Digital ground GND 10
Serial data 3 input SDIN3 11
Sony/Philips digital interface format input SPDIF_IN 12
Table 3-2. Digital Audio Output Interface (J3)
HEADER
SIGNAL NAME SCHEMATIC NET NAME
PIN ASSIGNMENT
Not connected NC 1
Not connected NC 2
Serial data 2 output SDOUT2 3
Digital ground GND 4
Serial data 1 output SDOUT1 5
Digital ground GND 6
Serial clock output SCLKOUT 7
Digital ground GND 8
Left/right clock output LRCLKOUT 9
Digital ground GND 10
Master clock output MCLKOUT 11
Digital ground GND 12
18 System Interfaces SLEU097 – April 2008
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