1.8V
SBCLK
FSYNC
SDIN
SDOUT
GND
SCL
SDZ
IRQZ
GND
GND
PDM Header
Soundwire Mode Settings
Mode Settings
PDMD
PDMCK
1.8V
GND
1
2
3
4
5
6
J11
SW-MODE-SEL
0.1µF
25V
C80
1µF
10V
C79
47.0k
R14
10.0k
R11
2.20k
R13
470
R12
SCL1
SDA1
SDZ
IRQZ
MODE
GND
FSYNC1
SCL1
SDA1
10.0k
R15
10.0k
R53
10.0k
R52
GND
1.8V
0.1µF
16V
C78
GND
3.3V
TP15
AVDD
J21
AVDD
TP24
IOVDD
J22
IOVDD
GND
0.1µF
25V
C64
AVDD
IOVDD
TDM/Control
Bus
GND
2.2µF
10V
C21
GND
1µF
10V
C46
TP25
PDMD
TP7
SDZ
TP8
IRQZ
TP5
SCL
TP1
SBCLK
TP4
SDOUT
TP3
SDIN
TP2
FSYNC
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
J13
MODE
MODE
TP12
GND
GND
TP13
GND
GND
I2C-SEL_CTRL
1A
A1
1B
B1
1C
B2
GND
D1
2A
D2
2B
C2
2C
C1
VCC
A2
U2
SN74LVC2G66YZPR
0.1µF
16V
C7
GND
3.3V
3.3V
GND
1A
A1
1B
B1
1C
B2
GND
D1
2A
D2
2B
C2
2C
C1
VCC
A2
U20
SN74LVC2G66YZPR
3.3V
GND
1A
A1
1B
B1
1C
B2
GND
D1
2A
D2
2B
C2
2C
C1
VCC
A2
U21
SN74LVC2G66YZPR
3.3V
SDA
TP6
SDA
3.3V
10.0k
R35
GND
J12
I2C-SEL
0.1µF
16V
C12
GND
3.3V
2
4
5
3
U23
LVC1G14
GND
FSYNC
SCL
SDA
I2C-SEL_CTRL
I2C-SEL_CTRL
I2C-SEL_CTRL
0.1µF
16V
C13
GND
3.3V
To
TDM/Control
Bus
3.3V
TP26
PDMCK
1
2
3
4
J8
PDM
SDIN
SDOUT
SBCLK
FSYNC1
PDMD
PDMCK
0.1µF
25V
C81
GND
GND
22µF
20V
C82
22µF
20V
C14
GND
TP14
VBAT
J18
VBAT
VBAT
VBAT-U1
GND
GND
GND
1µF
10V
C41
1µF
10V
C83
0.1µF
25V
C63
GND
0.1µF
25V
C62
GND
TP18
DREG
TP19
AREG
DREG
AREG
100pF
C17
0
R50
GND
GND
TP9
VSNS-P
TP10
VSNS-N
0.1µF
25V
C15
0.1µF
25V
C16
OUTPUT
0
R51
100pF
C39
VSNS-P
VSNS-N
TP16
OUTP
TP17
OUTN
OUTP
OUTN
J15
OUT+
J20
OUT-
BST-P
BST-N
J10
OUT
VSNS_P
A1
BST_P
B2
OUT_N
A5
PGND
A4
OUT_P
A3
VSNS_N
B1
BST_N
A2
OUT_N
B5
PGND
B4
OUT_P
B3
AVDD
C1
GND
C2
SDZ
C3
VBAT
C4
VBAT
C5
DREG
D1
IOVDD
D2
MODE
D3
IRQZ
D4
AREG
D5
SDOUT
E1
FSYNC
E2
GND
E3
GND
E4
PDMD
E5
SBCLK
F1
SDIN
F2
SDA
F3
SCL
F4
PDMCK
F5
TAS2770YFFR
U1
Copyright © 2017, Texas Instruments Incorporated
Hardware Documentation
13
SLOU500 – December 2017
Copyright © 2017, Texas Instruments Incorporated
TAS2770YFF Evaluation Module
Figure 10. Schematic: TAS2770YFF Channel 1 Control
