Texas Instruments Stellaris IDM-L35, Руководство пользователя

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Hardware Description
14 August 7, 2009
Functional Description
This section describes the IDM-L35’s hardware design in detail.
Microcontroller, Reset, and JTAG (Schematic page 1)
Page 1 of the schematics details the microcontroller, and JTAG debug interface.
Microcontroller
At the core of the IDM-L35 is the Stellaris LM3S1958 microcontroller (U1). The Stellaris
microcontroller operates at up to 50 MHz using an internal PLL.
The LM3S1958 microcontroller has an internal LDO voltage regulator that supplies power for
internal use. This rail requires only three capacitors for decoupling and is not connected to any
other circuits.
A reset switch (SW1) and R-C network (R25, C15) connect to the microcontroller’s RSTn input. An
external reset circuit is not required by the LM3S1958 microcontroller, the R-C components simply
serve to filter any noise on the reset line.
Debugging
The microcontroller supports JTAG and SWD debugging as well as SWO trace capabilities. To
minimize board area, the IDM-L35 uses a 0.050” pitch header (J6) which matches ARM’s
fine-pitch definition (Figure 2-2). Some in-circuit debuggers provide a matching connector. Other
debuggers can be used with the ADA1 adaptor board included in the RDK.
Figure 2-2. Debug Connection Pinout
LCD Panel and Voltage Regulators (Schematic page 2)
Page 2 of the schematics contains the LCD panel connector, 3.3 V DC regulator, and the high
voltage LED driver for the LCD panel backlight.
LCD Panel
The LCD panel is attached to FPC ZIF connector P1 and is a 3.5” TFT panel with an integrated
controller (SSD2119). The graphics display memory resides in the LCD panel and contains 168
kilobytes. The LCD panel requires only a 3.3 V power supply which also simplifies system design.
The LCD panel system interface has several modes of operation, for the IDM-L35 it is configured
for 8080 series 16-bit parallel interface mode for improved data rate. Only two control lines
(LCD_RDn, LCD_WRn) are required for reading and writing to the panel. A third signal (LCD_DC)
selects between memory and display control register access. In order to meet reset signal timing
requirements the microcontroller also controls the panel’s reset signal (LCD_RSTn).
1 2
9 10
TMS/ SWDIO
TCK/ SWCLK
TDO
TDI
SRSTn
3.3V
GND
GND
n/c
GND