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List of Figures

VLYNQ Port Functional Block Diagram

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External Clock Block Diagram

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Internal Clock Block Diagram

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VLYNQ Module Structure

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Write Operations

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Read Operations

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Example Address Memory Map

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Interrupt Generation Mechanism Block Diagram

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Revision Register (REVID)

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Control Register (CTRL)

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Status Register (STAT)

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Interrupt Priority Vector Status/Clear Register (INTPRI)

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Interrupt Status/Clear Register (INTSTATCLR)

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Interrupt Pending/Set Register (INTPENDSET)

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Interrupt Pointer Register (INTPTR)

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Transmit Address Map Register (XAM)

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Receive Address Map Size 1 Register (RAMS1)

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Receive Address Map Offset 1 Register (RAMO1)

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Receive Address Map Size 2 Register (RAMS2)

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Receive Address Map Offset 2 Register (RAMO2)

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Receive Address Map Size 3 Register (RAMS3)

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Receive Address Map Offset 3 Register (RAMO3)

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Receive Address Map Size 4 Register (RAMS4)

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Receive Address Map Offset 4 Register (RAMO4)

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Chip Version Register (CHIPVER)

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Auto Negotiation Register (AUTNGO)

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A-1

Packet Format (10-bit Symbol Representation)

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SPRU938B – September 2007

List of Figures

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Содержание SPRU938B

Страница 1: ...TMS320DM643x DMP VLYNQ Port User s Guide Literature Number SPRU938B September 2007 ...

Страница 2: ...2 SPRU938B September 2007 Submit Documentation Feedback ...

Страница 3: ...28 3 4 Interrupt Priority Vector Status Clear Register INTPRI 30 3 5 Interrupt Status Clear Register INTSTATCLR 30 3 6 Interrupt Pending Set Register INTPENDSET 31 3 7 Interrupt Pointer Register INTPTR 31 3 8 Transmit Address Map Register XAM 32 3 9 Receive Address Map Size 1 Register RAMS1 33 3 10 Receive Address Map Offset 1 Register RAMO1 33 3 11 Receive Address Map Size 2 Register RAMS2 34 3 1...

Страница 4: ... 39 A 4 VLYNQ 2 0 Packet Format 40 A 5 VLYNQ 2 X Packets 42 Appendix B Write Read Performance 44 B 1 Introduction 44 B 2 Write Performance 44 B 3 Read Performance 46 Appendix C Revision History 47 4 Contents SPRU938B September 2007 Submit Documentation Feedback ...

Страница 5: ...et Register INTPENDSET 31 15 Interrupt Pointer Register INTPTR 31 16 Transmit Address Map Register XAM 32 17 Receive Address Map Size 1 Register RAMS1 33 18 Receive Address Map Offset 1 Register RAMO1 33 19 Receive Address Map Size 2 Register RAMS2 34 20 Receive Address Map Offset 2 Register RAMO2 34 21 Receive Address Map Size 3 Register RAMS3 35 22 Receive Address Map Offset 3 Register RAMO3 35 ...

Страница 6: ...t 1 Register RAMO1 Field Descriptions 33 16 Receive Address Map Size 2 Register RAMS2 Field Descriptions 34 17 Receive Address Map Offset 2 Register RAMO2 Field Descriptions 34 18 Receive Address Map Size 3 Register RAMS3 Field Descriptions 35 19 Receive Address Map Offset 3 Register RAMO3 Field Descriptions 35 20 Receive Address Map Size 4 Register RAMS4 Field Descriptions 36 21 Receive Address M...

Страница 7: ...m Reference Guide Describes the digital signal processor DSP subsystem in the TMS320DM643x Digital Media Processor DMP SPRU983 TMS320DM643x DMP Peripherals Overview Reference Guide Provides an overview and briefly describes the peripherals available on the TMS320DM643x Digital Media Processor DMP SPRAA84 TMS320C64x to TMS320C64x CPU Migration Guide Describes migrating from the Texas Instruments TM...

Страница 8: ...dicate that overflow conditions might occur The VLYNQ module on the DM643x DMP serializes a write transaction to the remote external device and transfers the write via the VLYNQ port TX pins The remote VLYNQ module deserializes the transaction on the other side The read transactions to the remote external device follow the same process but the remote device s VLYNQ module serializes the read retur...

Страница 9: ... are all multiplexed and sent across the same physical pins Supports both host peripheral and peer to peer communication models Simple block code packet formatting 8b 10b Supports in band and flow control No extra pins are needed Allows the receiver to momentarily throttle the transmitter back when overflow is about to occur Uses the special built in block code capability to interleave flow contro...

Страница 10: ...register CTRL The VLYNQ serial clock can be sourced from the internal system clock CLKDIR 1 or by an external clock source CLKDIR 0 for its serial operations The CLKDIV bit can divide the serial clock 1 1 1 8 down when the internal clock is selected as the source The serial clock is not affected by the CLKDIV bit values if the serial clock is externally sourced The reset value of the CLKDIR bit is...

Страница 11: ...YNQ serial clock is requested to be high when all transactions are complete VLYNQ_RXD 0 3 VLYNQ receive data Input VLYNQ receive data is synchronous with the VLYNQ serial clock VLYNQ_TXD 0 3 VLYNQ transmit data Output VLYNQ transmit data is synchronous with the VLYNQ serial clock Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest pos...

Страница 12: ...YNQ Module Structure The VLYNQ core module implements two 32 bit configuration bus interfaces Transmit operations and control register access require the slave configuration bus interface The master configuration bus interface is required for receive operations Converting to and from the 32 bit bus to the external serial interface requires serializer and deserializer blocks 8b 10b block coding enc...

Страница 13: ...onfig bus interface Slave config bus interface Peripheral Architecture Write requests that initiate from the slave configuration bus interface of the local device write to the outbound command CMD FIFO Data is subsequently read from the FIFO and encapsulated in a write request packet The address is translated and the packet is encoded and serialized before being transmitted to remote device The re...

Страница 14: ...Data is subsequently read from the FIFO and encapsulated into a read request packet The packet is encoded and serialized before it is transmitted to the remote device Next the remote device deserializes decodes the receive data and writes the receive data to the inbound CMD FIFO After reading the address from the FIFO a master configuration bus interface read operation initiates in the remote devi...

Страница 15: ...n detected during a period of 4096 serial clock cycles Auto negotiation occurs after reset It involves placing a negotiation protocol in the outbound data and processing the inbound data to establish connection information The width of the data pins on the serial interface is automatically determined at reset as a part of the initialization sequence For a connection between two VLYNQ devices of ve...

Страница 16: ...Then the local device sends the data with an address offset from the transmit address VLYNQ allows each receive packet address to be translated into one of the four mapped regions The size and offset of each memory region must be aligned to 32 bit words No restriction is placed on programming the size or on the offset of each mapped region as long as the total memory that is mapped into these one ...

Страница 17: ... Map The following shows an example illustrating the address translation used in each VLYNQ module Address bits 31 26 are not used for address translation to remote devices on the DM643x device Table 2 shows the address map register configuration when the DM643x device is transmitting data to the remote device Table 2 Address Translation Example Single Mapped Region Register DM643x VLYNQ Module Re...

Страница 18: ...Module Remote VLYNQ Module TX Address Map Do not care 0400 0000h RX Address Map Size 1 0000 0100h Do not care RX Address Map Offset 1 0200 0000h Do not care RX Address Map Size 2 0000 0100h Do not care RX Address Map Offset 2 8200 0000h Do not care Remote VLYNQ Module 0400 0154h Initial address at the slave configuration bus for the remote device subtract 0400 0000h TX address map register 0000 01...

Страница 19: ...Map Size 1 Register RX Address Map Size 2 Register else if RX Packet Address RX Address Map Size 1 Register RX Address Map Size 2 Register RX Address Map Size 3 Register RX Address Map Size 4 Register Translated Address RX Packet Address RX Address Map Offset 4 Register RX Address Map Size 1 Register RX Address Map Size 2 Register RX Address Map Size 3 Register else Translated Address 0x0 The VLYN...

Страница 20: ...a transmission can resume CAUTION Be cautious when only resetting one of the VLYNQ devices after two or more VLYNQ devices have established a link If only one of the VLYNQ devices is in reset then no data activity can occur across the serial interface during the time of reset The VLYNQ module interrupt VLQINT is mapped to the interrupt controller INT55 For more information on the interrupt control...

Страница 21: ...and interprets bit 31 as the lowest priority The value that is returned when read is the vector of the highest priority interrupt Software can clear that interrupt by writing back the vector value Additionally INTRPRI provides a read only status bit NOINTPEND to indicate whether or not there are any pending interrupts in INTSTATCLR The VLYNQ interrupt generation mechanism is shown in Figure 8 Figu...

Страница 22: ...LYNQINT to be asserted to the CPU To ensure that serial bus errors result in interrupts to notify the application software you must perform the following steps 1 Set the INTENABLE bit to 1 in the VLYNQ control register CTRL 2 Set the INTVEC bits in CTRL to point to a free bit in the VLYNQ interrupt pending set register INTPENDSET The serial bus error should result in setting the bits in INTPENDSET...

Страница 23: ...ced you can use the CLKDIV bit in the VLYNQ control register CTRL to divide the serial clock down This saves normal mode operation power consumption at the expense of reduced performance Additionally the module provides the capability of auto idling the serial clock domain disable the VLYNQ CLK when the serial clock is sourced from the DM643x device and the VLYNQ SCRUN pin is connected to the remo...

Страница 24: ...en the two devices Table 5 VLYNQ Port Controller Registers Offset Acronym Register Description Section 0h REVID Revision Register Section 3 1 4h CTRL Control Register Section 3 2 8h STAT Status Register Section 3 3 Ch INTPRI Interrupt Priority Vector Status Clear Register Section 3 4 10h INTSTATCLR Interrupt Status Clear Register Section 3 5 14h INTPENDSET Interrupt Pending Set Register Section 3 ...

Страница 25: ...ure 9 Revision Register REVID 31 16 ID R 1h 15 8 7 0 REVMAJ REVMIN R 2h R 6h LEGEND R Read only n value after reset Table 6 Revision Register REVID Field Descriptions Bit Field Value Description 31 16 ID 01h Unique module ID 15 8 REVMAJ 0 FFh Major revision 2h Current major revision 7 0 REVMIN 0 FFh Minor revision 6h Current minor revision SPRU938B September 2007 VLYNQ Port 25 Submit Documentation...

Страница 26: ...rder to modify the value you must simultaneously write a 1 to the RTMVALIDWR bit 23 RTMVALIDWR RTM valid write bit 0 Will not allow writes to RXSAMPLEVAL bits 1 Will allow writes to RXSAMPLEVAL bits 22 RTMENABLE RTM enable bit The receive timing manager uses the value set in the RXSAMPLEVAL bit as the clock sample 0 value 1 The receive timing manager is enabled It automatically selects the receive...

Страница 27: ... a VLYNQ module local register typically the interrupt pending set register 6 3 Reserved 0 Reserved Always read as 0 Writes have no effect 2 AOPTDISABLE Address optimization disable 0 Address optimization is enabled eliminating unnecessary address bytes 1 Address optimization is disabled 1 ILOOP Internal loop back 0 Normal operation 1 Serial transmit data is wrapped back to the serial receive data...

Страница 28: ...X pins used 4h 4 RX pins used 5h Fh Reserved 23 20 SWIDTHOUT 0 Fh Size of the outbound serial data Indicates the number of transmit pins that are being used to establish the serial interface 0 No pins used 1h 1 TX pin used 2h 2 TX pins used 3h 3 TX pins used 4h 4 TX pins used 5h Fh Reserved 19 15 Reserved 0 Reserved Always read as 0 Writes have no effect 14 12 RXCURRENTSAMPLE 0 Fh Current RTM samp...

Страница 29: ...nd FIFO is not empty 5 NFEMPTY2 FIFO 2 is not empty 0 Indicates that the slave data FIFO is empty 1 Indicates that the slave data FIFO is not empty 4 NFEMPTY1 FIFO 1 is not empty 0 Indicates that the master command FIFO is empty 1 Indicates that the master command FIFO is not empty 3 NFEMPTY0 FIFO 0 is not empty 0 Indicates that the master data FIFO is empty 1 Indicates that the master data FIFO i...

Страница 30: ...r 30 5 Reserved 0 Reserved Always read as 0 Writes have no effect 4 0 INSTAT 0 1Fh When read this field displays the vector that is mapped to the highest priority interrupt bit that is pending from the interrupt status clear register INSTATCLR with bit 0 as the highest priority and bit 31 as the lowest Writing the vector value back to this field clears the interrupt The interrupt status clear regi...

Страница 31: ... 0 in CTRL interrupt packet is sent on the serial interface If INTLOCAL 1 in CTRL VLYNQ module interrupt VLQINT is asserted The interrupt pointer register INTPTR typically contains the address of the interrupt pending set register INTPENDSET within the VLYNQ module To program INTPTR to point to INTPENDSET program a value of 14h the offset of INTPENDSET Additionally the INT2CFG bit in the control r...

Страница 32: ... 0 TXADRMAP Reserved R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 13 Address Map Register XAM Field Descriptions Bit Field Value Description 31 2 TXADRMAP 0 3FFF FFFFh This field is subtracted from the slave configuration bus address 25 0 to obtain the zero relative transmit packet address This field should be programmed with a value of 0 reset value 1 0 Reserved 0 Reserve...

Страница 33: ...ddress map offset 1 register RAMO1 to obtain the translated address 1 0 Reserved 0 Reserved Always read as 0 Writes have no effect The receive address map offset 1 register RAMO1 is used with the receive address map size 1 register RAMS1 to translate receive packet addresses to local device configuration bus addresses The RAMO1 is shown in Figure 18 and described in Table 15 Figure 18 Receive Addr...

Страница 34: ...address map offset 2 register RAMO2 to obtain the translated address 1 0 Reserved 0 Reserved Always read as 0 Writes have no effect The receive address map offset 2 register RAMO2 is used with the receive address map size 2 register RAMS2 to translate receive packet addresses to local device configuration bus addresses The RAMO2 is shown in Figure 20 and described in Table 17 Figure 20 Receive Add...

Страница 35: ...ddress map offset 3 register RAMO3 to obtain the translated address 1 0 Reserved 0 Reserved Always read as 0 Writes have no effect The receive address map offset 3 register RAMO3 is used with the receive address map size 3 register RAMS3 to translate receive packet addresses to local device configuration bus addresses The RAMO3 is shown in Figure 22 and described in Table 19 Figure 22 Receive Addr...

Страница 36: ...address map offset 4 register RAMO4 to obtain the translated address 1 0 Reserved 0 Reserved Always read as 0 Writes have no effect The receive address map offset 4 register RAMO4 is used with the receive address map size 4 register RAMS4 to translate receive packet addresses to local device configuration bus addresses The RAMS4 is shown in Figure 24 and described in Table 21 Figure 24 Receive Add...

Страница 37: ... Read only n value after reset Table 22 Chip Version Register CHIPVER Field Descriptions Bit Field Value Description 31 16 DEVREV 0 FFFFh Device revision This field reflects the value of the device revision pins 15 0 DEVID 0 FFFFh Device ID 2Dh DM643x device ID The auto negotiation register AUTNGO reflects the ability of the VLYNQ module residing in the device to communicate with the remote VLYNQ ...

Страница 38: ... Remote Revision Register 84h RCTRL Remote Control Register 88h RSTAT Remote Status Register 8Ch RINTPRI Remote Interrupt Priority Vector Status Clear Register 90h RINTSTATCLR Remote Interrupt Status Clear Register 94h RINTPENDSET Remote Interrupt Pending Set Register 98h RINTPTR Remote Interrupt Pointer Register 9Ch RXAM Remote Transmit Address Map Register A0h RRAMS1 Remote Receive Address Map S...

Страница 39: ... 0101 K28 6 DC 1101 1100 001111 0110 110000 1001 K28 7 FC 1111 1100 001111 1000 110000 0111 K23 7 F7 1111 0111 111010 1000 000101 0111 K27 7 FB 1111 1011 110110 1000 001001 0111 K29 7 FD 1111 1101 101110 1000 010001 0111 K30 7 FE 1111 1110 011110 1000 100001 0111 Each VLYNQ module must support a limited number of ordered sets Ordered sets provide for the delineation of packets and synchronization ...

Страница 40: ...low control disable request is transmitted by a VLYNQ module when RX FIFO resources are available to accommodate additional data The error indication is transmitted when errors are detected within a packet Examples of such errors include illegal packet types and code groups The Init0 code group is used during the link initialization sequence VLYNQ 2 0 and later versions use this code with an extra...

Страница 41: ...included only if ADRMASK 0 is set to 1 If ADRMASK 0 is cleared to 0 assume this byte is equal to bits 7 0 of the previous address Read response packets do not include this field ADDRESS 15 8 Address byte 1 This byte is included only if ADRMASK 1 is set to 1 If ADRMASK 1 is cleared to 0 assume this byte is equal to bits 15 8 of the previous address Read response packets do not include this field AD...

Страница 42: ... a channel L Link pulse and what is in italics is optional data up to 16 words total Packet with byte enables WriteBurst claaaaMMddMMddMMddT The above packet wrote to the LS half words from the specified address Packet that has been flowed due to remote FIFO status WriteBurst claaaaMMddMIIIIIIIIIIIII MddMMddT The packet was extended using the I code The is used to indicate that the same channel wa...

Страница 43: ...ket is now under way A flow is now received for channel 1 but it is soon disabled so the channel 1 packet continues The flow is enabled for channel one again quickly after flow is released for channel 0 so the data continues for channel 0 when a flow is received again for channel 0 Channel 0 then receives a flow disable completes its packet followed by channel 1 flow disable where the channel 1 pa...

Страница 44: ...4 pin per direction interface the raw data is 99 4 or 396 Mbps After the 8B10B encoding is removed the maximum write rate is 396 0 8 316 8 Mbps The total throughput on the VLYNQ interface includes both transmit and receive directions Therefore for the above configuration a remote device can also be writing to the local device at the same data rates then the total throughput is the sum of transmit ...

Страница 45: ... Mbits sec Mbytes sec Mbits sec Mbytes sec 1 1 24 19 3 02 31 68 3 96 4 42 07 5 26 55 09 6 89 8 49 62 6 20 64 98 8 12 16 54 52 6 81 71 39 8 92 2 1 48 38 6 05 63 36 7 92 4 84 14 10 52 110 18 13 77 8 99 25 12 41 129 97 16 25 16 109 03 13 63 142 78 17 85 3 1 72 58 9 07 95 04 11 88 4 126 21 15 78 165 27 20 66 8 148 87 18 61 194 95 24 37 16 163 55 20 44 214 17 26 77 4 1 96 77 12 10 126 72 15 84 4 168 28...

Страница 46: ...ices is combined Read Throughput data Read ReadReturn data max read rate Latency data max read rate Read ReadReturn data Latency max read rate For example with a 4 pin 99 MHZ VLYNQ connection for a single 32 bit word read Read Throughput 32 bits 316 8 Mbps 6 8 3 8 4 8 Latency 316 8Mbps 10137 6 104 Latency 316 8 Mbps Similarly for a burst read of sixteen 32 bit words with a 4 pin 99 MHZ VLYNQ conne...

Страница 47: ...his document Table C 1 Document Revision History Reference Additions Modifications Deletions Section 2 8 Changed fourth paragraph Added NOTE Section 3 17 Changed paragraph Figure 25 Changed DEVID reset value Table 22 Changed DEVID Description SPRU938B September 2007 Revision History 47 Submit Documentation Feedback ...

Страница 48: ...ice and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyer...

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