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Texas Instruments SLAU081, Руководство пользователя

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Texas Instruments SLAU081 Скачать руководство пользователя страница 18

Connectors

2-9

Getting Started

Reference

Designator

Description

Pin

Number

Function

J7

EVM power

1

5 V

2

–12 V

3

0 V

4

12 V

J8

Analog output option,

1

No output

g

,

26-pin DIL header

2

AGND

3

Analog output for one-channel DAC

4

AGND

5

Not connected

6

AGND

7

Not connected

8

AGND

9

Not connected

10

AGND

11

Not connected

12

AGND

13

Not connected

14

AGND

15

Not connected

16

AGND

17

Not connected

18

AGND

19

Not connected

20

AGND

21

Not connected

22

AGND

23

Not connected

24

AGND

25

Not connected

26

AGND

Содержание SLAU081

Страница 1: ... January 2002 AAP Data Acquisition Dallas User s Guide SLAU081 ...

Страница 2: ...nt that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or end...

Страница 3: ... handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR A...

Страница 4: ...ere is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is designed to operate properly with certain components above 60 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors p...

Страница 5: ...t Configuration 2 2 2 2 Jumpers 2 4 2 2 1 Analog I O Signal Conditioning 2 4 2 2 2 Channel 0 Analog Input 2 4 2 2 3 Channel 0 Analog Output 2 5 2 2 4 Signal Generator 2 5 2 2 5 Voltage Reference 2 5 2 2 6 ADC Supply Voltage 2 5 2 2 7 Clock Timer Routing 2 6 2 3 Switches 2 6 2 3 1 Stand Alone Mode SW1 1 2 6 2 4 Connectors 2 7 2 5 ADC and DAC Direct Access 2 11 2 6 Host Communication 2 11 2 6 1 Comm...

Страница 6: ...Running Title Attribute Reference vi Figures 2 1 SAM Configuration 2 2 Tables 2 1 Default Switch Settings 2 3 2 2 Default Jumper Settings 2 3 2 3 Jumper Function Reference 2 4 ...

Страница 7: ...uction This chapter contains an overview of the features and functions of the EVM Topic Page 1 1 EVM Modes 1 2 1 2 Analog Input Conditioning 1 3 1 3 Analog Output Conditioning 1 3 1 4 Prototype Area 1 3 Chapter 1 ...

Страница 8: ... Chapter 2 describes the operation of the EVM from a user s view It details options that can be modified connectors used and pinout details Appendix A details the bill of materials BOM and the schematic along with explanations of certain EVM features 1 1 EVM Modes This EVM has been designed tested and shipped in a condition that enables the user to begin evaluation with minimal effort There are ba...

Страница 9: ... is off For example TI s range of DSP starter kits DSK modules provides a simple low cost solution offering a range of DSK modules for most needs The EVM also supports the TMS320C6000 daughtercard specification SPRA711 in addition to providing support for the Motorola specification for data transfer SPI 1 2 Analog Input Conditioning There are a number of methods to connect analog input signals to ...

Страница 10: ...pter describes how the user can modify the various options of this EVM Topic Page 2 1 Shipping Default Configuration 2 2 2 2 Jumpers 2 4 2 3 Switches 2 6 2 4 Connectors 2 7 2 5 ADC and DAC Direct Access 2 11 2 6 Host Communication 2 11 Chapter 2 ...

Страница 11: ...W3 5 Press the start button SW2 6 Check TP20 with an oscilloscope If the system is working properly the signal at TP20 will also be a sine wave The system works as illustrated below Any analog input supplied to the ADC will be digitized and reconstructed by the DAC Figure 2 1 SAM Configuration ADC DAC Control Electronics DSP Micro Interface Data Data TP20 TP7 The user may probe the data and contro...

Страница 12: ...erted SCLK routed to ADC W11 Not inserted Inserted Signal conditioning output selected for channel 0 W12 Inserted Not inserted FS routed to ADC W13 Not Inserted 5 V analog W14 Inserted EVM reference or DAC s on chip reference selected W15 Not populated Not populated W16 Inserted Not inserted Selects internal or external reference W17 Inserted Not inserted Determines EVM reference voltage W18 Not i...

Страница 13: ...channel configured with a gain of 1 Use the prototype area for signal conditioning Use the expansion connector via a TI universal operational amplifier evaluation module such as SLOP224 SLOP249 2 2 2 Channel 0 Analog Input This is the primary analog input and can always be connected externally Analog Input Configuration Channel 0 Reference Designator Functional Description W1 W1 allows the user to...

Страница 14: ...t signals A jumper installed between pins 1 and 2 disables the waveform generator 2 2 5 Voltage Reference Voltage Reference Reference Designator Functional Description W16 W16 selects either the onboard reference or an external reference supplied by the user W17 W17 allows the user to vary the reference voltage W14 There are a number of possible DACs that a user can install on this EVM Some have a...

Страница 15: ...There are three switches present on the EVM One 8 pin DIL switch which houses four individual switches these are denoted SW1 1 SW1 2 SW1 3 and SW1 4 Two momentary push button switches Features and functions of each switch Reference Designator Function Default Condition SW1 1 Selects either stand alone mode SAM or user mode SAM SW1 2 Reserved SW1 3 Reserved SW1 4 Reserved 2 3 1 Stand Alone Mode SW1...

Страница 16: ...operational amplifier 2 g for universal operational amplifier 2 Noninverting input signal to dual operational amplifier 2 operational amplifier evaluation board SIL 3 Inverting input signal to dual operational amplifier 2 evaluation board SIL PTH not installed 4 Inverting input signal to dual operational amplifier 2 5 Nonfiltered output from dual operational amplifier 2 6 Filtered output from dual...

Страница 17: ...AGND 5 Not connected 6 AGND 7 Not connected 8 AGND 9 Not connected 10 AGND 11 Not connected 12 AGND 13 Not connected 14 AGND 15 Not connected 16 AGND 17 Not connected 18 AGND 19 Not connected 20 AGND 21 Not connected 22 AGND 23 Not connected 24 AGND 25 External reference voltage 26 AGND Reference Designator Description J5 Analog output for one channel DAC ...

Страница 18: ... No output g 26 pin DIL header 2 AGND 3 Analog output for one channel DAC 4 AGND 5 Not connected 6 AGND 7 Not connected 8 AGND 9 Not connected 10 AGND 11 Not connected 12 AGND 13 Not connected 14 AGND 15 Not connected 16 AGND 17 Not connected 18 AGND 19 Not connected 20 AGND 21 Not connected 22 AGND 23 Not connected 24 AGND 25 Not connected 26 AGND ...

Страница 19: ... operational amplifier 2 5 Nonfiltered output from dual operational amplifier 2 6 Filtered output from dual operational amplifier 2 7 V supply 8 Operational amplifier 2 shutdown signal 9 Reference voltage 10 Analog ground 11 Operational amplifier 1 shutdown signal 12 V supply 13 Nonfiltered output from dual operational amplifier 1 14 Filtered output from dual operational amplifier 1 15 Noninvertin...

Страница 20: ...l ground 8 FS J11 Allows the user direct access to all digital signals for the DAC 1 Digital ground g g 2 SDI 3 Digital ground 4 SCLK 5 Digital ground 6 CS 7 Digital ground 8 FS 2 6 Host Communication There are two ways to connect a host system DSP microprocessor Texas Instruments new DSKs provide two dedicated 80 pin connectors The EVM can be plugged directly onto these DSKs This connector standa...

Страница 21: ... connector for C5000 and C6000 DSK 1 5 V y EVMs Pins unused by this EVM are omitted for clarity 2 5 V 11 PCI ground 12 PCI ground 21 5 V 22 5 V 29 PCI ground 30 PCI ground 31 PCI ground 32 PCI ground 41 3 3 V 42 3 3 V 51 PCI ground 52 PCI ground 61 PCI ground 62 PCI ground 71 PCI ground 72 PCI ground 79 PCI ground 80 PCI ground ...

Страница 22: ...s EVM are omitted for clarity 2 12 V 3 PCI ground 4 PCI ground 5 5 V 6 5 V 7 PCI ground 8 PCI ground 9 5 V 10 5 V 35 FSX 33 CLKX 36 DX 25 PCI ground 26 PCI ground 39 CLKR 41 FSR 42 DR 31 PCI ground 32 PCI ground 37 PCI ground 38 PCI ground 43 PCI ground 44 PCI ground 45 TOUT 49 XF 51 PCI ground 52 PCI ground 61 PCI ground 62 PCI ground 76 PCI ground 77 PCI ground 79 PCI ground 80 PCI ground ...

Страница 23: ...directly onto the appropriate header For example if the host connector on the DSP has the pin assignment described in the following table then a 1 1 mapping is possible and the user should plug a flat 20 way ribbon cable into J13 Host Connector EVM Connector J13 Pin No Signal Pin No Signal Pin No Signal Pin No Signal 1 XF 2 DGND 1 XF 2 DGND 3 CLKX 4 DGND 3 CLKX 4 DGND 5 CLKR 6 DGND 5 CLKR 6 DGND 7...

Страница 24: ...13 NA 14 DGND 15 XF 16 DGND 17 NA 18 NA 19 NA 20 CLKS The host connector mates with J12 Signals on either side of J12 are available on J13 and J15 J13 Host Connector Plugged into J12 J15 Pin No Pin No Signal Pin No Signal Pin No 2 1 N A 2 DGND 1 4 3 N A 4 DGND 3 6 5 CLKX 6 CLKR 5 8 7 TOUT 8 DGND 7 10 9 DX 10 DR 9 12 11 FSX 12 FSR 11 14 13 N A 14 DGND 13 16 15 XF 16 DGND 15 18 17 N A 18 N A 17 20 1...

Страница 25: ...DGND 4 NA 3 DGND 6 CLKX 5 CLKR 8 TOUT 7 DGND 10 DX 9 DR 12 FSX 11 FSR 14 NA 13 DGND 16 XF 15 DGND 18 NA 17 NA 20 NA 19 CLKS The table below shows the signal names and pin assignments that the composite connector shown above must be mapped onto J13 Pin No Signal 1 XF 3 CLKX 5 CLKR 7 DX 9 DR 11 FSX 13 FSR 15 Resvd 17 CLKS 19 TOUT ...

Страница 26: ... J13 Pin No Signal Pin No Signal 2 NA 4 NA 6 CLKX 3 CLKX 8 TOUT 19 TOUT 10 DX 7 DX 12 FSX 11 FSX 14 NA 16 XF 1 XF 18 NA 20 NA J15 Wire Wrap J13 Jumper B t J15 Pin No Signal Pin No Signal Between Pin No Signal 1 DGND YES 2 DGND 3 DGND YES 4 DGND 5 CLKR YES 5 CLKR 6 DGND 7 DGND YES 8 DGND 9 DR YES 9 DR 10 DGND 11 FSR YES 13 FSR 12 DGND 13 DGND YES 14 DGND 15 DGND YES 16 DGND 17 NA 18 DGND 19 CLKS YE...

Страница 27: ...er Signal Name Function J12 20 pin connector 1 J13 pin 2 2 J15 pin 1 3 J13 pin 4 4 J15 pin 3 5 J13 pin 6 6 J15 pin 5 7 J13 pin 8 8 J15 pin 7 9 J13 pin 10 10 J15 pin 9 11 J13 pin 12 12 J15 pin 11 13 J13 pin 14 14 J15 pin 13 15 J13 pin 16 16 J15 pin 15 17 J13 pin 18 18 J15 pin 17 19 J13 pin 20 20 J15 pin 19 ...

Страница 28: ...DC select signal 2 J12 pin 1 3 CLKX transmit clock 4 J12 pin 3 5 CLKR receive clock 6 J12 pin 5 7 DX data transmit 8 J12 pin 7 9 DR data receive 10 J12 pin 9 11 FSX frame sync transmit 12 J12 pin 11 13 FSR frame sync receive 14 J12 pin 13 15 Reserved 16 J12 pin 15 17 CLKS sync clock 18 J12 pin 17 19 TOUT host timer output 20 J12 pin 19 ...

Страница 29: ...Pin Number Signal Name Function J15 20 Pin connector 1 J12 pin 2 2 DGND 3 J12 pin 4 4 DGND 5 J12 pin 6 6 DGND 7 J12 pin 8 8 DGND 9 J12 pin 10 10 DGND 11 J12 pin 12 12 DGND 13 J12 pin 14 14 DGND 15 J12 pin 16 16 DGND 17 J12 pin 18 18 DGND 19 J12 pin 20 20 DGND ...

Страница 30: ...A 1 Bill of Materials Board Layout and Schematics Bill of Materials Board Layout and Schematics This appendix contains the bill of materials board layouts and the EVM schematics Appendix A ...

Страница 31: ... SENSE VREFP SENSE VREFP In_0 ADC_Data_out VREFP SENSE In_1 LCL_CLKX FS LCL_CS_ADC ADC AOUT VREFP DAC_Data_in AOUT_A DAC_Write LCL_CS_DAC LCL_CLKX DAC PCI_GND PCI_ 12V PCI_ 12V DSP_CLKX DSP_FSX DSP_CLKR DSP_FSR DSP_XF DSP_DX DSP_DR DSP_TOUT DSP_CLKS PCI_ 5v User connectors ADC_Data_out DAC_Data_in FS LCL_CS_DAC LCL_CS_ADC LCL_CLKX DSP_XF DSP_DX DSP_CLKX DSP_FSX DSP_DR DSP_FSR DSP_CLKR DSP_CLKS DSP...

Страница 32: ...ference DATE 28 Nov 2001 Power Reference 6430333 A4 Supply Ground Supply VIN REF_IN VIN Vs Vs DVdd DVdd Power VREFP EXT_VREFP 1 2 3 FL4 1 2 3 FL2 1 2 3 FL3 1 2 3 FL1 R69 0 R68 0 R70 0 PCI_ 12V PCI_ 12V PCI_GND VIN VREFP EXT_REFP SENSE Reference SENSE C10 10uF C11 10uF VS VS GND GND GND C57 10uF C56 10uF 5V_IN DVdd 2 040500 R58 0 PCI_ 5v FB13 SM_FB_27 044447 GND Joe Purvis Joe Purvis ...

Страница 33: ...N 3 IN 4 PG 8 SENSE FB 7 OUT 6 OUT 5 ENA 2 GND 1 U6 TPS77801D D2 C26 4 7uF D1 Green R17 1K C27 0 1uF R18 20K R63 357K R64 110K R24 590K C31 4 7uF C51 4 7uF C34 0 1uF C53 0 1uF C50 0 01uF TP16 TP18 C24 4 7uF C28 0 1uF C29 0 01uF TP9 TP11 Vs Vs TP12 TP13 C59 10uF C44 10uF C58 0 1uF C42 10uF C20 10uF AVdd DVdd R62 0 C25 10uF C33 10uF W13 DVdd F 040500 R14 0 FB1 BLM11A121SGPB FB3 BLM11A121SGPB FB2 BLM...

Страница 34: ... 4 14 Reference DATE 28 Nov 2001 Reference 6430333 A4 VIN VREFP W16 EXT_REFP TP10 RV9 10k R29 10K W17 R66 4k R65 6k R67 10K Vin 2 NR 8 REF GND 7 GND 4 TRIM 5 Vout 6 Temp 3 U7 VRE3050 C30 2 2uF C38 2 2uF RV7 10k SENSE Vs Vs C45 0 1uF C46 0 1uF Vout 6 V 7 Trim 1 Trim 5 In 2 In 3 V 4 U11 TLE2081 R20 0 R23 0 RV10 100K R50 5K F 040500 R25 Not Installed Joe Purvis Joe Purvis ...

Страница 35: ...01 ADC 6430333 A4 In_0 ADC_Data_out C19 10uF C22 0 1uF AVdd VREFP SENSE R19 0 In_1 W10 W12 CS or CS FS 1 Vref 2 AGND 3 AIN or AIN0 or AIN 4 SCLK or AIN1 or AIN 5 VDD 6 FS or SCLK 7 SDO 8 U5 LCL_CLKX FS LCL_CS_ADC SOCKETED ADC C23 10uF C14 0 1uF C47 0 01uF 1 2 3 4 5 6 7 8 U501 ADC_REF ADC_REF AIN0 AIN1 AIN0 AIN1 MSOP ADC R10 10K C1 100pF DVdd 040500 2 1 2 3 4 5 6 7 8 J10 Joe Purvis Joe Purvis ...

Страница 36: ...T OUTB 7 REF 6 AGND 5 Vcc 8 DIN 1 U8 SOCKETED DAC W18 B204 1 B203 2 B202 3 B201 4 B2_OUT 5 B2_FLT 6 B2 SD 8 A201 18 A2 SD 11 A202 17 A203 16 A2_OUT 13 A2_FLT 14 A204 15 V2 7 V2 12 VREF2 9 GND 10 J9 W15 C41 10uF C43 0 1uF AVdd AOUT W19 OUTA DAC_OUTA DAC Out OUT OUTB DAC_OUT DAC Out DAC_Write LCL_CS_DAC LCL_CLKX W14 C32 0 1uF C21 0 1uF 2 3 4 7 6 5 8 1 U801 DAC SOP D AVdd REF REF VS VS R54 10K R55 10...

Страница 37: ...4 Output conditioning DATE 28 Nov 2001 DAC Output 6430333 A4 Vs Vs RV11 100K R35 4 7K C52 R31 NI DAC_OUTA OUTA Vs Vs RV8 100K R26 4 7K C36 R22 NI DAC_OUT OUT OUTB R21 0 R34 0 C40 0 1uF C48 0 1uF C49 0 1uF C39 0 1uF Vout 6 V 7 Trim 1 Trim 5 In 2 In 3 V 4 U9 R27 0 R28 0 R51 5K Vout 6 V 7 Trim 1 Trim 5 In 2 In 3 V 4 U12 TLE2081 R30 0 R32 0 R33 0 2 040500 Joe Purvis Joe Purvis ...

Страница 38: ...14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 J17 5v Peripheral Control Connector Memory Interface Connector 5v 3 3v CLKX FSX CLKR 3 3v FSR XF DX DR TOUT CLKS FB8 BLM11A121SGPB FB10 BLM11A121SGPB FB7 BLM11A121SGPB FB6 BLM11A121SGPB XF FB9 BLM11A...

Страница 39: ...n 2 SW1B Out 6 In 3 SW1C DVdd DAC_Type Out 5 In 4 SW1D R38 1K R37 1K C65 0 1uF OE 1 GND 4 OUT 5 VCC 8 X1 FS LCL_CS_DAC LCL_CS_ADC LCL_CLKX DSP_XF DSP_DX DSP_CLKX DSP_FSX DSP_DR DSP_FSR DSP_CLKR DSP_CLKS DSP_TOUT DSP_TOUT DSP_CLKS DSP_CLKR DSP_FSR DSP_CLKX DSP_DX DSP_XF DSP_DR DSP_FSX DAC_Write TO FROM USER CONNECTIONS TO FROM ADC TO DAC W23 W20 W21 SYSCLK W24 EVM_CLKX R71 33 EVM_CLKX C64 0 01uF D4...

Страница 40: ... I18 O6 Q6 24 I19 O7 Q7 25 I20 O8 Q8 26 I21 O9 Q9 27 NC 1 NC 8 NC 15 NC 22 U16A I11 16 I10 13 I9 12 I8 11 I7 10 I6 9 I5 7 I4 6 I3 5 I2 4 I1 3 CLK I0 2 I12 O0 Q0 17 I13 O1 Q1 18 I14 O2 Q2 19 I15 O3 Q3 20 I16 O4 Q4 21 I17 O5 Q5 23 I18 O6 Q6 24 I19 O7 Q7 25 I20 O8 Q8 26 I21 O9 Q9 27 NC 1 NC 8 NC 15 NC 22 U13A I11 16 I10 13 I9 12 I8 11 I7 10 I6 9 I5 7 I4 6 I3 5 I2 4 I1 3 CLK I0 2 I12 O0 Q0 17 I13 O1 Q...

Страница 41: ...C_0 B204 1 B203 2 B202 3 B201 4 B2_OUT 5 B2_FLT 6 B2 SD 8 A201 18 A2 SD 11 A202 17 A203 16 A2_OUT 13 A2_FLT 14 A204 15 V2 7 V2 12 VREF2 9 GND 10 J3 W5 BNC_1 IDC_1 Channel_1 Vs Vs Channel_0 Test signal 0 Test signal 1 Signal Generator TP6 R12 33 C9 6800pF TP7 R9 33 C8 6800pF W3 BB_Output_1 IN_1 Prototype Area W8 W6 BB_Output_0 IN_0 Prototype Area IN_0 OUT_0 Signal Conditioning W7 W2 OUT_1 IN_1 Sign...

Страница 42: ...0 Sine Out 2 Triangle Out 3 Square Out 9 V 6 Duty adj 5 Duty Adj 4 Timing Cap 10 V GND 11 Sine Adj 1 Sine Adj 12 FM Bias 7 FM Sweep Input 8 Not connected 13 Not Connected 14 U3 ICL8038 R72 49 9K W9 RV3 100K R7 4 7K C13 0 1uF C12 0 1uF C6 10uF C5 0 1uF C15 0 1uF Vs RV4 10K TP5 Vs Test Signal 1 RV6 100K R15 4 7K C7 0 1uF Vs RV5 10K TP8 3 2 1 8 4 U4A TLE2082D 5 6 7 U4B TLE2082D C16 0 1uF Vs C18 10uF ...

Страница 43: ...I Boulevard Dallas Texas 75243 TITLE SHEET OF FILE SIZE REV Drawn By Engineer DOCUMENT CONTROL 13 14 Prototype Area DATE 28 Nov 2001 Prototype Area 6430333 A4 BB_Output_1 IN_1 BB_Output_0 IN_0 TP1 TP2 TP3 TP4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PT1 2 040500 Joe Purvis Joe Purvis ...

Страница 44: ... CONTROL 14 14 Signal Conditioning DATE 28 Nov 2001 Signal Conditioning 6430333 A4 OUT_1 IN_1 R3 NI R4 0 Vs Vs RV2 100K OUT_0 IN_0 R1 NI R2 0 Vs Vs RV1 100K C37 0 1uF C4 0 1uF C2 0 1uF C3 0 1uF Vout 6 V 7 Trim 1 Trim 5 In 2 In 3 V 4 U2 TLE2081 R36 0 R47 0 R52 5K Vout 6 V 7 Trim 1 Trim 5 In 2 In 3 V 4 U1 TLE2081 R48 0 R49 0 R53 5K F 040500 Joe Purvis Joe Purvis ...

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