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9.12 Power Management
To minimize power consumption, the CC2652PSIP supports a number of power modes and power management
features (see
Table 9-1 ).
Table 9-1. Power Modes
MODE
SOFTWARE CONFIGURABLE POWER MODES
RESET PIN
HELD
ACTIVE IDLE STANDBY SHUTDOWN
CPU Active Off Off Off Off
Flash On Available Off Off Off
SRAM On On Retention Off Off
Supply System On On Duty Cycled Off Off
Register and CPU retention Full Full Partial No No
SRAM retention Full Full Full No No
48 MHz high-speed clock
(SCLK_HF) XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off Off Off
2 MHz medium-speed clock
(SCLK_MF)
RCOSC_MF RCOSC_MF Available Off Off
32 kHz low-speed clock
(SCLK_LF) XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Off Off
Peripherals Available Available Off Off Off
Sensor Controller Available Available Available Off Off
Wake-up on RTC Available Available Available Off Off
Wake-up on pin edge Available Available Available Available Off
Wake-up on reset pin On On On On On
Brownout detector (BOD) On On Duty Cycled Off Off
Power-on reset (POR) On On On Off Off
Watchdog timer (WDT) Available Available Paused Off Off
In Active mode, the application system CPU is actively executing code. Active mode provides normal operation
of the processor and all of the peripherals that are currently enabled. The system clock can be any available
clock source (see
Table 9-1 ).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked
and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor
Controller event is required to bring the device back to active mode. MCU peripherals with retention do not need
to be reconfigured when waking up again, and the CPU continues execution from where it went into standby
mode. All GPIOs are latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and
the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O
pin defined as a
wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can
differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status
register. The only state retained in this mode is the latched I/O state and the flash memory contents.
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CC2652PSIP
SWRS263A – FEBRUARY 2021 – REVISED JUNE 2022
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