Texas Instruments SimpleLink CC2652PSIP, Руководство пользователя

Страница: 24 / 68

T
c
= 25 °C, V
DDS
= 3.0 V and voltage scaling enabled, unless otherwise noted.
(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input impedance
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance depends on sampling frequency and sampling
time
>1 MΩ
(1) Using IEEE Std 1241-2010 for terminology and test methods
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
(3) Applied voltage must be within Absolute Maximum Ratings (see Section 8.1 ) at all times
(4) No missing codes
(5) ADC_output = Σ(4
n
samples ) >> n, n = desired extra bits
8.15.2 DAC
8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
T
c
= 25 °C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Resolution 8 Bits
V
DDS
Supply voltage
Any load, any V
REF
, pre-charge OFF, DAC charge-pump ON 1.8 3.8
V
External Load
(4)
, any V
REF
, pre-charge OFF, DAC charge-pump
OFF
2.0 3.8
Any load, V
REF
= DCOUPL, pre-charge ON 2.6 3.8
F
DAC
Clock frequency
Buffer ON (recommended for external load) 16 250
kHz
Buffer OFF (internal load) 16 1000
Voltage output settling time
V
REF
= VDDS, buffer OFF, internal load 13
1 / F
DAC
V
REF
= VDDS, buffer ON, external capacitive load = 20 pF
(3)
13.8
External capacitive load 20 200 pF
External resistive load 10 MΩ
Short circuit current 400 µA
Z
MAX
Max output impedance Vref =
VDDS, buffer ON, CLK 250
kHz
VDDS = 3.8 V, DAC charge-pump OFF 51.1
kΩ
VDDS = 3.0 V, DAC charge-pump ON 53.1
VDDS = 3.0 V, DAC charge-pump OFF 54.3
VDDS = 2.0 V, DAC charge-pump ON 48.7
VDDS = 2.0 V, DAC charge-pump OFF 70.2
VDDS = 1.8 V, DAC charge-pump ON 49.4
VDDS = 1.8 V, DAC charge-pump OFF 79.2
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
DNL
Differential nonlinearity
V
REF
= VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
F
DAC
= 250 kHz
±1
LSB
(1)
Differential nonlinearity
V
REF
= VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
F
DAC
= 16 kHz
±1.2
Offset error
(2)
Load = Continuous Time
Comparator
V
REF
= VDDS = 3.8 V ±0.64
LSB
(1)
V
REF
= VDDS= 3.0 V ±0.81
V
REF
= VDDS = 1.8 V ±1.27
V
REF
= DCOUPL, pre-charge ON ±3.43
V
REF
= DCOUPL, pre-charge OFF ±2.88
V
REF
= ADCREF ±2.37
CC2652PSIP
SWRS263A – FEBRUARY 2021 – REVISED JUNE 2022
www.ti.com
24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CC2652PSIP