Controlling the PGA450-Q1 Memory Spaces With the GUI
10
SLDU007C – March 2012 – Revised November 2015
Copyright © 2012–2015, Texas Instruments Incorporated
PGA450Q1EVM User’s Guide
8.2
ESFR Registers
The ESFR register displays all the function registers that are specific to PGA450-Q1 functionality. The
user can set each register manually through SPI or define register values in 8051W firmware. An
Evaluation
tab on the right side helps to set the ESFR registers for quick evaluation. More details of the
Evaluation
tab are described in a later section.
8.3
EEPROM Registers
The EEPROM in the PGA450-Q1 device comprises 32 bytes of EEPROM and an EEPROM cache. When
the EEPROM grid is updated in the GUI, only the cache is updated.
8.3.1
Program EEPROM
The
Program EEPROM
button writes 0x01 to the EE_CTRL ESFR to program the EEPROM memory
cells. The EEPROM memory cells are programmed with the values that are in the EEPROM cache inside
the PGA450-Q1 device.
The contents in the GUI are first transferred to the cache and then the cache is programmed.
8.3.2
Reload EEPROM
The
Reload EEPROM
button reloads the EEPROM cache inside the PGA450-Q1 device with the values in
the EEPROM memory cells. It then performs a READ ALL to update the grid with the refreshed contents
of the EEPROM bank.
The contents of the EEPROM cache can be updated on the GUI by clicking on the READ SELECTED or
READ ALL button.
8.4
RAM
The RAM tab is set up only for individual register read/writes without the use of the grid. When this tab is
displayed, the READ SELECTED / READ ALL and WRITE SELECTED / WRITE ALL buttons perform the
same operations, respectively.
The PGA450-Q1 device has 512 bytes of general-purpose RAM. This general-purpose RAM is memory-
mapped into two different memory spaces inside the PGA450-Q1 device: internal memory space
(0x00–0xFF) and external memory space (0x0300–0x03FF).
The user must select the appropriate memory space in the Combo Box before making the Read/Write
request. Note the valid address range for the two RAM sections.
8.5
OTP
The OTP tab is set up only for individual register read/writes without the use of the grid. When this tab is
displayed, the READ SELECTED / READ ALL and WRITE SELECTED / WRITE ALL buttons perform the
same operations, respectively. The OTP tab also contains buttons used to load a .HEX 8051 program file
into the 8051 MCU in the PGA450-Q1 device.
The PGA450Q1EVM could potentially have two devices: a device that is soldered on the EVM and a
device that is in the socket. The GUI allows programming of either device. When the device choice is
made, the GUI automatically resets the microprocessor for the respective device so that it is ready to load
OTP through SPI
NOTE:
The OTP program requires R2 to be populated and the VPWR:VOTP jumper to be installed.
This connects the VPROG_OTP 8-V supply on the VP_OTP pin during programming. See
the data sheet for more details.
