Software
11
SLDU019B – December 2015 – Revised March 2016
Copyright © 2015–2016, Texas Instruments Incorporated
PGA450Q1EVM-S User's Guide and TIDA-00151 UART Demo Instructional
?pr?external1_ISR?PGA450_isrs (0X2100),
?pr?timer0_ISR?PGA450_isrs (0X2400),
?pr?timer1_ISR?PGA450_isrs (0X2800),
?pr?serial_ISR?PGA450_isrs (0X2C00),
?pr?linPID_ISR?PGA450_isrs (0X3000),
?pr?linSciRxData_ISR?PGA450_isrs (0X3400),
?pr?linSciTxData_ISR?PGA450_isrs (0X3800),
?pr?external0_ISR?PGA450_isrs (0X3900),
?pr?linSync_ISR?PGA450_isrs (0X3D00)
Step 3.
Comment out the OTP section in STARTUP.A51, and remove the comments from the
DEVRAM section.
3.1.2
Setup for OTP Output File
Use the steps that follow to setup the output file of the OTP memory.
1. Change the code range to the OTP memory space:
1. Right click on
Target 1
in the project window, and select
Options for Target
.
2. Go to the BL51 Locate tab, and modify the Code Range to go from 0x0000–0x1FFF.
2. Delete everything in the Code box.
3. Comment out the DEVRAM section in STARTUP.A51, and remove the comments from the OTP
section.
3.2
Interface Descriptions
The PGA450-Q1 device is compatible with three communication interface options including: SPI, LIN, and
UART. All of these communication interfaces, related circuitry, or access points are integrated or present
on the PGA450Q1EVM-S.
3.2.1
UART Interface
The TxD and RxD pins on the PGA450-Q1 device are connected to the 8051W UART. These two pins
can be used either for software debugging or for implementing application-specific protocols. For a
detailed example of how to use UART with the PGA450-Q1 device, refer to
.
3.2.2
LIN Interface
The PGA450Q1EVM GUI can communicate with the PGA450-Q1 device using LIN. The UART of the TI
GER USB communication board is the LIN master, and the PGA450-Q1 device is the LIN slave. The GUI
can be used to configure the LIN frames that are transmitted to the PGA450-Q1 device. An external LIN
transceiver is required to translate the UART of the TI GER board into the LIN compliant format. For a
detailed example of how to use LIN with the PGA450-Q1 device, refer to
LIN Demonstration using
PGA450Q1EVM Firmware Rev 2.1
).
3.2.3
Serial-Peripheral Interface
The PGA450-Q1 device can also be put into a RESET state where the microcontroller is not active. During
this state, SPI is the only digital interface that can be used. The low-side drivers can still be triggered to
begin an ultrasonic burst and the analog front-end and digital data path can still store the returned echo
signal in the FIFO RAM. However, any processing of the FIFO RAM by the internal microprocessor to
determine the location of an object does not occur. The FIFO RAM data can be read over SPI, allowing an
external microprocessor to process the data.
To provide a quick evaluation of the performance of the PGA450-Q1 device using the PGA450Q1EVM-S
and GUI without having to develop sophisticated 8051
μ
P software, the GUI provides an intuitive interface
tab, the Evaluation Tab, that collects all required information regarding the transducer drive and receive.
For the transducer drive, it includes: transducer frequency; transducer drive voltage, VREG; transformer
configuration; and number of drive pulses. For the transducer signal receive, it includes signal-processing
parameters: LNA gain setting; BPF and LPF coefficient; clock selection; FIFO mode; and FIFO
downsample size.
