User's Guide
SBOU073 – February 2009
PGA112 Evaluation Module
This user’s guide describes the characteristics, operation, and use of the PGA112 evaluation module
(EVM). It covers all pertinent areas involved to properly use this EVM board. The document includes the
physical printed circuit board layout, schematic diagrams, and circuit descriptions.
Contents
1
2
System Setup
3
PGA112EVM Hardware Setup
.............................................................................................
4
PGA112 Software Overview
..............................................................................................
5
Bill of Materials
List of Figures
1
Hardware Included with the PGA112EVM
................................................................................
2
PGA112EVM Hardware Setup
.............................................................................................
3
PGA112_Test_Board Block Diagram
.....................................................................................
4
PGA112_Test_Board Schematic
..........................................................................................
5
USB_DAQ_Platform Block Diagram
......................................................................................
6
Typical Hardware Connections
...........................................................................................
7
Connecting the Two EVM PCBs
.........................................................................................
8
Connecting Power to the EVM
...........................................................................................
9
Connecting the USB Cable
...............................................................................................
10
PGA112EVM Default Jumper Settings
..................................................................................
11
PGA112EVM Software—Functioning Properly
.........................................................................
12
PGA112EVM Software—No Communication With the USB DAQ Platform
........................................
13
Scaled Inputs to PGA112/113
............................................................................................
14
Selection of Internal Reference or DAC Reference
....................................................................
15
PGA112/113 Bit Read Tables
............................................................................................
16
PGA112 Measurement Module Tab
.....................................................................................
17
PGA112/113 Self-Test Function
..........................................................................................
List of Tables
1
Signal Definition of J1 (25-Pin Male DSUB) on PGA112_Test_Board
...............................................
2
Signal Definition of J2 (25-Pin Female DSUB) on PGA112_Test_Board
............................................
3
PGA112_Test_Board Jumper Functions
................................................................................
4
USB DAQ Platform Jumper Settings
....................................................................................
5
PGA112_Test_Board Parts List
..........................................................................................
Microsoft, Windows are registered trademarks of Microsoft Corporation.
SPI is a trademark of Motorola Inc.
I
2
C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
SBOU073 – February 2009
PGA112 Evaluation Module
1